CC1200: Radiated Immunity Issues

// Rf settings for CC1200
RF_SETTINGS code rfSettings = {
    0x06,  // IOCFG3                GPIO3 IO Pin Configuration
    0x06,  // IOCFG2                GPIO2 IO Pin Configuration
    0x30,  // IOCFG1                GPIO1 IO Pin Configuration
    0x3C,  // IOCFG0                GPIO0 IO Pin Configuration
    0x93,  // SYNC3                 Sync Word Configuration [31:24]
    0x0B,  // SYNC2                 Sync Word Configuration [23:16]
    0x51,  // SYNC1                 Sync Word Configuration [15:8]
    0xDE,  // SYNC0                 Sync Word Configuration [7:0]
    0xAB,  // SYNC_CFG1             Sync Word Detection Configuration Reg. 1
    0x13,  // SYNC_CFG0             Sync Word Detection Configuration Reg. 0
    0x8D,  // DEVIATION_M           Frequency Deviation Configuration
    0x00,  // MODCFG_DEV_E          Modulation Format and Frequency Deviation Configur..
    0x4C,  // DCFILT_CFG            Digital DC Removal Configuration
    0x14,  // PREAMBLE_CFG1         Preamble Length Configuration Reg. 1
    0x8A,  // PREAMBLE_CFG0         Preamble Detection Configuration Reg. 0
    0xC8,  // IQIC                  Digital Image Channel Compensation Configuration
    0x95,  // CHAN_BW               Channel Filter Configuration
    0x42,  // MDMCFG1               General Modem Parameter Configuration Reg. 1
    0x05,  // MDMCFG0               General Modem Parameter Configuration Reg. 0
    0x70,  // SYMBOL_RATE2          Symbol Rate Configuration Exponent and Mantissa [1..
    0x62,  // SYMBOL_RATE1          Symbol Rate Configuration Mantissa [15:8]
    0x4E,  // SYMBOL_RATE0          Symbol Rate Configuration Mantissa [7:0]
    0x1F,  // AGC_REF               AGC Reference Level Configuration
    0xEE,  // AGC_CS_THR            Carrier Sense Threshold Configuration
    0x00,  // AGC_GAIN_ADJUST       RSSI Offset Configuration
    0xB1,  // AGC_CFG3              Automatic Gain Control Configuration Reg. 3
    0x20,  // AGC_CFG2              Automatic Gain Control Configuration Reg. 2
    0x11,  // AGC_CFG1              Automatic Gain Control Configuration Reg. 1
    0x94,  // AGC_CFG0              Automatic Gain Control Configuration Reg. 0
    0x00,  // FIFO_CFG              FIFO Configuration
    0x00,  // DEV_ADDR              Device Address Configuration
    0x0B,  // SETTLING_CFG          Frequency Synthesizer Calibration and Settling Con..
    0x12,  // FS_CFG                Frequency Synthesizer Configuration
    0x08,  // WOR_CFG1              eWOR Configuration Reg. 1
    0x21,  // WOR_CFG0              eWOR Configuration Reg. 0
    0x00,  // WOR_EVENT0_MSB        Event 0 Configuration MSB
    0x00,  // WOR_EVENT0_LSB        Event 0 Configuration LSB
    0x00,  // RXDCM_TIME            RX Duty Cycle Mode Configuration
    0x00,  // PKT_CFG2              Packet Configuration Reg. 2
    0x03,  // PKT_CFG1              Packet Configuration Reg. 1
    0x20,  // PKT_CFG0              Packet Configuration Reg. 0
    0x0F,  // RFEND_CFG1            RFEND Configuration Reg. 1
    0x00,  // RFEND_CFG0            RFEND Configuration Reg. 0
    0x7F,  // PA_CFG1               Power Amplifier Configuration Reg. 1
    0x55,  // PA_CFG0               Power Amplifier Configuration Reg. 0
    0x0F,  // ASK_CFG               ASK Configuration
    0xFF,  // PKT_LEN               Packet Length Configuration
    0x1C,  // IF_MIX_CFG            IF Mix Configuration
    0x20,  // FREQOFF_CFG           Frequency Offset Correction Configuration
    0x03,  // TOC_CFG               Timing Offset Correction Configuration
    0x00,  // MARC_SPARE            MARC Spare
    0x00,  // ECG_CFG               External Clock Frequency Configuration
    0x02,  // MDMCFG2               General Modem Parameter Configuration Reg. 2
    0x01,  // EXT_CTRL              External Control Configuration
    0x00,  // RCCAL_FINE            RC Oscillator Calibration Fine
    0x00,  // RCCAL_COARSE          RC Oscillator Calibration Coarse
    0x00,  // RCCAL_OFFSET          RC Oscillator Calibration Clock Offset
    0x00,  // FREQOFF1              Frequency Offset MSB
    0x00,  // FREQOFF0              Frequency Offset LSB
    0x56,  // FREQ2                 Frequency Configuration [23:16]
    0xCC,  // FREQ1                 Frequency Configuration [15:8]
    0xCC,  // FREQ0                 Frequency Configuration [7:0]
    0x02,  // IF_ADC2               Analog to Digital Converter Configuration Reg. 2
    0xEE,  // IF_ADC1               Analog to Digital Converter Configuration Reg. 1
    0x10,  // IF_ADC0               Analog to Digital Converter Configuration Reg. 0
    0x04,  // FS_DIG1               Frequency Synthesizer Digital Reg. 1
    0x50,  // FS_DIG0               Frequency Synthesizer Digital Reg. 0
    0x00,  // FS_CAL3               Frequency Synthesizer Calibration Reg. 3
    0x20,  // FS_CAL2               Frequency Synthesizer Calibration Reg. 2
    0x40,  // FS_CAL1               Frequency Synthesizer Calibration Reg. 1
    0x0E,  // FS_CAL0               Frequency Synthesizer Calibration Reg. 0
    0x28,  // FS_CHP                Frequency Synthesizer Charge Pump Configuration
    0x03,  // FS_DIVTWO             Frequency Synthesizer Divide by 2
    0x00,  // FS_DSM1               FS Digital Synthesizer Module Configuration Reg. 1
    0x33,  // FS_DSM0               FS Digital Synthesizer Module Configuration Reg. 0
    0xF7,  // FS_DVC1               Frequency Synthesizer Divider Chain Configuration ..
    0x0F,  // FS_DVC0               Frequency Synthesizer Divider Chain Configuration ..
    0x00,  // FS_LBI                Frequency Synthesizer Local Bias Configuration
    0x00,  // FS_PFD                Frequency Synthesizer Phase Frequency Detector Con..
    0x6E,  // FS_PRE                Frequency Synthesizer Prescaler Configuration
    0x1C,  // FS_REG_DIV_CML        Frequency Synthesizer Divider Regulator Configurat..
    0xAC,  // FS_SPARE              Frequency Synthesizer Spare
    0x14,  // FS_VCO4               FS Voltage Controlled Oscillator Configuration Reg..
    0x00,  // FS_VCO3               FS Voltage Controlled Oscillator Configuration Reg..
    0x00,  // FS_VCO2               FS Voltage Controlled Oscillator Configuration Reg..
    0x00,  // FS_VCO1               FS Voltage Controlled Oscillator Configuration Reg..
    0xB5,  // FS_VCO0               FS Voltage Controlled Oscillator Configuration Reg..
    0x00,  // GBIAS6                Global Bias Configuration Reg. 6
    0x02,  // GBIAS5                Global Bias Configuration Reg. 5
    0x00,  // GBIAS4                Global Bias Configuration Reg. 4
    0x00,  // GBIAS3                Global Bias Configuration Reg. 3
    0x10,  // GBIAS2                Global Bias Configuration Reg. 2
    0x00,  // GBIAS1                Global Bias Configuration Reg. 1
    0x00,  // GBIAS0                Global Bias Configuration Reg. 0
    0x09,  // IFAMP                 Intermediate Frequency Amplifier Configuration
    0x01,  // LNA                   Low Noise Amplifier Configuration
    0x01,  // RXMIX                 RX Mixer Configuration
    0x0E,  // XOSC5                 Crystal Oscillator Configuration Reg. 5
    0xA0,  // XOSC4                 Crystal Oscillator Configuration Reg. 4
    0x03,  // XOSC3                 Crystal Oscillator Configuration Reg. 3
    0x04,  // XOSC2                 Crystal Oscillator Configuration Reg. 2
    0x03,  // XOSC1                 Crystal Oscillator Configuration Reg. 1
    0x00,  // XOSC0                 Crystal Oscillator Configuration Reg. 0
    0x00,  // ANALOG_SPARE          Analog Spare
    0x00,  // PA_CFG3               Power Amplifier Configuration Reg. 3
    0x00,  // WOR_TIME1             eWOR Timer Counter Value MSB
    0x00,  // WOR_TIME0             eWOR Timer Counter Value LSB
    0x00,  // WOR_CAPTURE1          eWOR Timer Capture Value MSB
    0x00,  // WOR_CAPTURE0          eWOR Timer Capture Value LSB
    0x00,  // BIST                  MARC Built-In Self-Test
    0x00,  // DCFILTOFFSET_I1       DC Filter Offset I MSB
    0x00,  // DCFILTOFFSET_I0       DC Filter Offset I LSB
    0x00,  // DCFILTOFFSET_Q1       DC Filter Offset Q MSB
    0x00,  // DCFILTOFFSET_Q0       DC Filter Offset Q LSB
    0x00,  // IQIE_I1               IQ Imbalance Value I MSB
    0x00,  // IQIE_I0               IQ Imbalance Value I LSB
    0x00,  // IQIE_Q1               IQ Imbalance Value Q MSB
    0x00,  // IQIE_Q0               IQ Imbalance Value Q LSB
    0x80,  // RSSI1                 Received Signal Strength Indicator Reg. 1
    0x00,  // RSSI0                 Received Signal Strength Indicator Reg.0
    0x41,  // MARCSTATE             MARC State
    0x00,  // LQI_VAL               Link Quality Indicator Value
    0xFF,  // PQT_SYNC_ERR          Preamble and Sync Word Error
    0x00,  // DEM_STATUS            Demodulator Status
    0x00,  // FREQOFF_EST1          Frequency Offset Estimate MSB
    0x00,  // FREQOFF_EST0          Frequency Offset Estimate LSB
    0x00,  // AGC_GAIN3             Automatic Gain Control Reg. 3
    0xD1,  // AGC_GAIN2             Automatic Gain Control Reg. 2
    0x00,  // AGC_GAIN1             Automatic Gain Control Reg. 1
    0x3F,  // AGC_GAIN0             Automatic Gain Control Reg. 0
    0x00,  // CFM_RX_DATA_OUT       Custom Frequency Modulation RX Data
    0x00,  // CFM_TX_DATA_IN        Custom Frequency Modulation TX Data
    0x30,  // ASK_SOFT_RX_DATA      ASK Soft Decision Output
    0x7F,  // RNDGEN                Random Number Generator Value
    0x00,  // MAGN2                 Signal Magnitude after CORDIC [16]
    0x00,  // MAGN1                 Signal Magnitude after CORDIC [15:8]
    0x00,  // MAGN0                 Signal Magnitude after CORDIC [7:0]
    0x00,  // ANG1                  Signal Angular after CORDIC [9:8]
    0x00,  // ANG0                  Signal Angular after CORDIC [7:0]
    0x02,  // CHFILT_I2             Channel Filter Data Real Part [16]
    0x00,  // CHFILT_I1             Channel Filter Data Real Part [15:8]
    0x00,  // CHFILT_I0             Channel Filter Data Real Part [7:0]
    0x00,  // CHFILT_Q2             Channel Filter Data Imaginary Part [16]
    0x00,  // CHFILT_Q1             Channel Filter Data Imaginary Part [15:8]
    0x00,  // CHFILT_Q0             Channel Filter Data Imaginary Part [7:0]
    0x00,  // GPIO_STATUS           General Purpose Input/Output Status
    0x01,  // FSCAL_CTRL            Frequency Synthesizer Calibration Control
    0x00,  // PHASE_ADJUST          Frequency Synthesizer Phase Adjust
    0x00,  // PARTNUMBER            Part Number
    0x00,  // PARTVERSION           Part Revision
    0x00,  // SERIAL_STATUS         Serial Status
    0x01,  // MODEM_STATUS1         Modem Status Reg. 1
    0x00,  // MODEM_STATUS0         Modem Status Reg. 0
    0x00,  // MARC_STATUS1          MARC Status Reg. 1
    0x00,  // MARC_STATUS0          MARC Status Reg. 0
    0x00,  // PA_IFAMP_TEST         Power Amplifier Intermediate Frequency Amplifier T..
    0x00,  // FSRF_TEST             Frequency Synthesizer Test
    0x00,  // PRE_TEST              Frequency Synthesizer Prescaler Test
    0x00,  // PRE_OVR               Frequency Synthesizer Prescaler Override
    0x00,  // ADC_TEST              Analog to Digital Converter Test
    0x0B,  // DVC_TEST              Digital Divider Chain Test
    0x40,  // ATEST                 Analog Test
    0x00,  // ATEST_LVDS            Analog Test LVDS
    0x00,  // ATEST_MODE            Analog Test Mode
    0x3C,  // XOSC_TEST1            Crystal Oscillator Test Reg. 1
    0x00,  // XOSC_TEST0            Crystal Oscillator Test Reg. 0
    0x00,  // AES                   AES
    0x00,  // MDM_TEST              MODEM Test
    0x00,  // RXFIRST               RX FIFO Pointer First Entry
    0x00,  // TXFIRST               TX FIFO Pointer First Entry
    0x00,  // RXLAST                RX FIFO Pointer Last Entry
    0x00,  // TXLAST                TX FIFO Pointer Last Entry
    0x00,  // NUM_TXBYTES           TX FIFO Status
    0x00,  // NUM_RXBYTES           RX FIFO Status
    0x0F,  // FIFO_NUM_TXBYTES      TX FIFO Status
    0x00,  // FIFO_NUM_RXBYTES      RX FIFO Status
    0x00,  // RXFIFO_PRE_BUF        RX FIFO Status
    0x00,  // AES_KEY15             Advanced Encryption Standard Key [127:120]
    0x00,  // AES_KEY14             Advanced Encryption Standard Key [119:112]
    0x00,  // AES_KEY13             Advanced Encryption Standard Key [111:104]
    0x00,  // AES_KEY12             Advanced Encryption Standard Key [103:96]
    0x00,  // AES_KEY11             Advanced Encryption Standard Key [95:88]
    0x00,  // AES_KEY10             Advanced Encryption Standard Key [87:80]
    0x00,  // AES_KEY9              Advanced Encryption Standard Key [79:72]
    0x00,  // AES_KEY8              Advanced Encryption Standard Key [71:64]
    0x00,  // AES_KEY7              Advanced Encryption Standard Key [63:56]
    0x00,  // AES_KEY6              Advanced Encryption Standard Key [55:48]
    0x00,  // AES_KEY5              Advanced Encryption Standard Key [47:40]
    0x00,  // AES_KEY4              Advanced Encryption Standard Key [39:32]
    0x00,  // AES_KEY3              Advanced Encryption Standard Key [31:24]
    0x00,  // AES_KEY2              Advanced Encryption Standard Key [23:16]
    0x00,  // AES_KEY1              Advanced Encryption Standard Key [15:8]
    0x00,  // AES_KEY0              Advanced Encryption Standard Key [7:0]
    0x00,  // AES_BUFFER15          Advanced Encryption Standard Buffer [127:120]
    0x00,  // AES_BUFFER14          Advanced Encryption Standard Buffer [119:112]
    0x00,  // AES_BUFFER13          Advanced Encryption Standard Buffer [111:104]
    0x00,  // AES_BUFFER12          Advanced Encryption Standard Buffer [103:93]
    0x00,  // AES_BUFFER11          Advanced Encryption Standard Buffer [95:88]
    0x00,  // AES_BUFFER10          Advanced Encryption Standard Buffer [87:80]
    0x00,  // AES_BUFFER9           Advanced Encryption Standard Buffer [79:72]
    0x00,  // AES_BUFFER8           Advanced Encryption Standard Buffer [71:64]
    0x00,  // AES_BUFFER7           Advanced Encryption Standard Buffer [63:56]
    0x00,  // AES_BUFFER6           Advanced Encryption Standard Buffer [55:48]
    0x00,  // AES_BUFFER5           Advanced Encryption Standard Buffer [47:40]
    0x00,  // AES_BUFFER4           Advanced Encryption Standard Buffer [39:32]
    0x00,  // AES_BUFFER3           Advanced Encryption Standard Buffer [31:24]
    0x00,  // AES_BUFFER2           Advanced Encryption Standard Buffer [23:16]
    0x00,  // AES_BUFFER1           Advanced Encryption Standard Buffer [15:8]
    0x00,  // AES_BUFFER0           Advanced Encryption Standard Buffer [7:0]
};

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<body><table border=1 cellpadding=5 cellspacing=0>
<caption>CC1200 registers</caption>
<tr><th>Name</th><th>Address</th><th>Value</th>
<th>Description</th></tr><tr><td>IOCFG3<td>0x0000</td><td>0x06</td><td>GPIO3 IO Pin Configuration</td></tr>
<tr><td>IOCFG2<td>0x0001</td><td>0x06</td><td>GPIO2 IO Pin Configuration</td></tr>
<tr><td>IOCFG1<td>0x0002</td><td>0x30</td><td>GPIO1 IO Pin Configuration</td></tr>
<tr><td>IOCFG0<td>0x0003</td><td>0x3C</td><td>GPIO0 IO Pin Configuration</td></tr>
<tr><td>SYNC3<td>0x0004</td><td>0x93</td><td>Sync Word Configuration [31:24]</td></tr>
<tr><td>SYNC2<td>0x0005</td><td>0x0B</td><td>Sync Word Configuration [23:16]</td></tr>
<tr><td>SYNC1<td>0x0006</td><td>0x51</td><td>Sync Word Configuration [15:8]</td></tr>
<tr><td>SYNC0<td>0x0007</td><td>0xDE</td><td>Sync Word Configuration [7:0]</td></tr>
<tr><td>SYNC_CFG1<td>0x0008</td><td>0xAB</td><td>Sync Word Detection Configuration Reg. 1</td></tr>
<tr><td>SYNC_CFG0<td>0x0009</td><td>0x13</td><td>Sync Word Detection Configuration Reg. 0</td></tr>
<tr><td>DEVIATION_M<td>0x000A</td><td>0x8D</td><td>Frequency Deviation Configuration</td></tr>
<tr><td>MODCFG_DEV_E<td>0x000B</td><td>0x00</td><td>Modulation Format and Frequency Deviation Configur..</td></tr>
<tr><td>DCFILT_CFG<td>0x000C</td><td>0x4C</td><td>Digital DC Removal Configuration</td></tr>
<tr><td>PREAMBLE_CFG1<td>0x000D</td><td>0x14</td><td>Preamble Length Configuration Reg. 1</td></tr>
<tr><td>PREAMBLE_CFG0<td>0x000E</td><td>0x8A</td><td>Preamble Detection Configuration Reg. 0</td></tr>
<tr><td>IQIC<td>0x000F</td><td>0xC8</td><td>Digital Image Channel Compensation Configuration</td></tr>
<tr><td>CHAN_BW<td>0x0010</td><td>0x95</td><td>Channel Filter Configuration</td></tr>
<tr><td>MDMCFG1<td>0x0011</td><td>0x42</td><td>General Modem Parameter Configuration Reg. 1</td></tr>
<tr><td>MDMCFG0<td>0x0012</td><td>0x05</td><td>General Modem Parameter Configuration Reg. 0</td></tr>
<tr><td>SYMBOL_RATE2<td>0x0013</td><td>0x70</td><td>Symbol Rate Configuration Exponent and Mantissa [1..</td></tr>
<tr><td>SYMBOL_RATE1<td>0x0014</td><td>0x62</td><td>Symbol Rate Configuration Mantissa [15:8]</td></tr>
<tr><td>SYMBOL_RATE0<td>0x0015</td><td>0x4E</td><td>Symbol Rate Configuration Mantissa [7:0]</td></tr>
<tr><td>AGC_REF<td>0x0016</td><td>0x1F</td><td>AGC Reference Level Configuration</td></tr>
<tr><td>AGC_CS_THR<td>0x0017</td><td>0xEE</td><td>Carrier Sense Threshold Configuration</td></tr>
<tr><td>AGC_GAIN_ADJUST<td>0x0018</td><td>0x00</td><td>RSSI Offset Configuration</td></tr>
<tr><td>AGC_CFG3<td>0x0019</td><td>0xB1</td><td>Automatic Gain Control Configuration Reg. 3</td></tr>
<tr><td>AGC_CFG2<td>0x001A</td><td>0x20</td><td>Automatic Gain Control Configuration Reg. 2</td></tr>
<tr><td>AGC_CFG1<td>0x001B</td><td>0x11</td><td>Automatic Gain Control Configuration Reg. 1</td></tr>
<tr><td>AGC_CFG0<td>0x001C</td><td>0x94</td><td>Automatic Gain Control Configuration Reg. 0</td></tr>
<tr><td>FIFO_CFG<td>0x001D</td><td>0x00</td><td>FIFO Configuration</td></tr>
<tr><td>DEV_ADDR<td>0x001E</td><td>0x00</td><td>Device Address Configuration</td></tr>
<tr><td>SETTLING_CFG<td>0x001F</td><td>0x0B</td><td>Frequency Synthesizer Calibration and Settling Con..</td></tr>
<tr><td>FS_CFG<td>0x0020</td><td>0x12</td><td>Frequency Synthesizer Configuration</td></tr>
<tr><td>WOR_CFG1<td>0x0021</td><td>0x08</td><td>eWOR Configuration Reg. 1</td></tr>
<tr><td>WOR_CFG0<td>0x0022</td><td>0x21</td><td>eWOR Configuration Reg. 0</td></tr>
<tr><td>WOR_EVENT0_MSB<td>0x0023</td><td>0x00</td><td>Event 0 Configuration MSB</td></tr>
<tr><td>WOR_EVENT0_LSB<td>0x0024</td><td>0x00</td><td>Event 0 Configuration LSB</td></tr>
<tr><td>RXDCM_TIME<td>0x0025</td><td>0x00</td><td>RX Duty Cycle Mode Configuration</td></tr>
<tr><td>PKT_CFG2<td>0x0026</td><td>0x00</td><td>Packet Configuration Reg. 2</td></tr>
<tr><td>PKT_CFG1<td>0x0027</td><td>0x03</td><td>Packet Configuration Reg. 1</td></tr>
<tr><td>PKT_CFG0<td>0x0028</td><td>0x20</td><td>Packet Configuration Reg. 0</td></tr>
<tr><td>RFEND_CFG1<td>0x0029</td><td>0x0F</td><td>RFEND Configuration Reg. 1</td></tr>
<tr><td>RFEND_CFG0<td>0x002A</td><td>0x00</td><td>RFEND Configuration Reg. 0</td></tr>
<tr><td>PA_CFG1<td>0x002B</td><td>0x7F</td><td>Power Amplifier Configuration Reg. 1</td></tr>
<tr><td>PA_CFG0<td>0x002C</td><td>0x55</td><td>Power Amplifier Configuration Reg. 0</td></tr>
<tr><td>ASK_CFG<td>0x002D</td><td>0x0F</td><td>ASK Configuration</td></tr>
<tr><td>PKT_LEN<td>0x002E</td><td>0xFF</td><td>Packet Length Configuration</td></tr>
<tr><td>IF_MIX_CFG<td>0x2F00</td><td>0x1C</td><td>IF Mix Configuration</td></tr>
<tr><td>FREQOFF_CFG<td>0x2F01</td><td>0x20</td><td>Frequency Offset Correction Configuration</td></tr>
<tr><td>TOC_CFG<td>0x2F02</td><td>0x03</td><td>Timing Offset Correction Configuration</td></tr>
<tr><td>MARC_SPARE<td>0x2F03</td><td>0x00</td><td>MARC Spare</td></tr>
<tr><td>ECG_CFG<td>0x2F04</td><td>0x00</td><td>External Clock Frequency Configuration</td></tr>
<tr><td>MDMCFG2<td>0x2F05</td><td>0x02</td><td>General Modem Parameter Configuration Reg. 2</td></tr>
<tr><td>EXT_CTRL<td>0x2F06</td><td>0x01</td><td>External Control Configuration</td></tr>
<tr><td>RCCAL_FINE<td>0x2F07</td><td>0x00</td><td>RC Oscillator Calibration Fine</td></tr>
<tr><td>RCCAL_COARSE<td>0x2F08</td><td>0x00</td><td>RC Oscillator Calibration Coarse</td></tr>
<tr><td>RCCAL_OFFSET<td>0x2F09</td><td>0x00</td><td>RC Oscillator Calibration Clock Offset</td></tr>
<tr><td>FREQOFF1<td>0x2F0A</td><td>0x00</td><td>Frequency Offset MSB</td></tr>
<tr><td>FREQOFF0<td>0x2F0B</td><td>0x00</td><td>Frequency Offset LSB</td></tr>
<tr><td>FREQ2<td>0x2F0C</td><td>0x56</td><td>Frequency Configuration [23:16]</td></tr>
<tr><td>FREQ1<td>0x2F0D</td><td>0xCC</td><td>Frequency Configuration [15:8]</td></tr>
<tr><td>FREQ0<td>0x2F0E</td><td>0xCC</td><td>Frequency Configuration [7:0]</td></tr>
<tr><td>IF_ADC2<td>0x2F0F</td><td>0x02</td><td>Analog to Digital Converter Configuration Reg. 2</td></tr>
<tr><td>IF_ADC1<td>0x2F10</td><td>0xEE</td><td>Analog to Digital Converter Configuration Reg. 1</td></tr>
<tr><td>IF_ADC0<td>0x2F11</td><td>0x10</td><td>Analog to Digital Converter Configuration Reg. 0</td></tr>
<tr><td>FS_DIG1<td>0x2F12</td><td>0x04</td><td>Frequency Synthesizer Digital Reg. 1</td></tr>
<tr><td>FS_DIG0<td>0x2F13</td><td>0x50</td><td>Frequency Synthesizer Digital Reg. 0</td></tr>
<tr><td>FS_CAL3<td>0x2F14</td><td>0x00</td><td>Frequency Synthesizer Calibration Reg. 3</td></tr>
<tr><td>FS_CAL2<td>0x2F15</td><td>0x20</td><td>Frequency Synthesizer Calibration Reg. 2</td></tr>
<tr><td>FS_CAL1<td>0x2F16</td><td>0x40</td><td>Frequency Synthesizer Calibration Reg. 1</td></tr>
<tr><td>FS_CAL0<td>0x2F17</td><td>0x0E</td><td>Frequency Synthesizer Calibration Reg. 0</td></tr>
<tr><td>FS_CHP<td>0x2F18</td><td>0x28</td><td>Frequency Synthesizer Charge Pump Configuration</td></tr>
<tr><td>FS_DIVTWO<td>0x2F19</td><td>0x03</td><td>Frequency Synthesizer Divide by 2</td></tr>
<tr><td>FS_DSM1<td>0x2F1A</td><td>0x00</td><td>FS Digital Synthesizer Module Configuration Reg. 1</td></tr>
<tr><td>FS_DSM0<td>0x2F1B</td><td>0x33</td><td>FS Digital Synthesizer Module Configuration Reg. 0</td></tr>
<tr><td>FS_DVC1<td>0x2F1C</td><td>0xF7</td><td>Frequency Synthesizer Divider Chain Configuration ..</td></tr>
<tr><td>FS_DVC0<td>0x2F1D</td><td>0x0F</td><td>Frequency Synthesizer Divider Chain Configuration ..</td></tr>
<tr><td>FS_LBI<td>0x2F1E</td><td>0x00</td><td>Frequency Synthesizer Local Bias Configuration</td></tr>
<tr><td>FS_PFD<td>0x2F1F</td><td>0x00</td><td>Frequency Synthesizer Phase Frequency Detector Con..</td></tr>
<tr><td>FS_PRE<td>0x2F20</td><td>0x6E</td><td>Frequency Synthesizer Prescaler Configuration</td></tr>
<tr><td>FS_REG_DIV_CML<td>0x2F21</td><td>0x1C</td><td>Frequency Synthesizer Divider Regulator Configurat..</td></tr>
<tr><td>FS_SPARE<td>0x2F22</td><td>0xAC</td><td>Frequency Synthesizer Spare</td></tr>
<tr><td>FS_VCO4<td>0x2F23</td><td>0x14</td><td>FS Voltage Controlled Oscillator Configuration Reg..</td></tr>
<tr><td>FS_VCO3<td>0x2F24</td><td>0x00</td><td>FS Voltage Controlled Oscillator Configuration Reg..</td></tr>
<tr><td>FS_VCO2<td>0x2F25</td><td>0x00</td><td>FS Voltage Controlled Oscillator Configuration Reg..</td></tr>
<tr><td>FS_VCO1<td>0x2F26</td><td>0x00</td><td>FS Voltage Controlled Oscillator Configuration Reg..</td></tr>
<tr><td>FS_VCO0<td>0x2F27</td><td>0xB5</td><td>FS Voltage Controlled Oscillator Configuration Reg..</td></tr>
<tr><td>GBIAS6<td>0x2F28</td><td>0x00</td><td>Global Bias Configuration Reg. 6</td></tr>
<tr><td>GBIAS5<td>0x2F29</td><td>0x02</td><td>Global Bias Configuration Reg. 5</td></tr>
<tr><td>GBIAS4<td>0x2F2A</td><td>0x00</td><td>Global Bias Configuration Reg. 4</td></tr>
<tr><td>GBIAS3<td>0x2F2B</td><td>0x00</td><td>Global Bias Configuration Reg. 3</td></tr>
<tr><td>GBIAS2<td>0x2F2C</td><td>0x10</td><td>Global Bias Configuration Reg. 2</td></tr>
<tr><td>GBIAS1<td>0x2F2D</td><td>0x00</td><td>Global Bias Configuration Reg. 1</td></tr>
<tr><td>GBIAS0<td>0x2F2E</td><td>0x00</td><td>Global Bias Configuration Reg. 0</td></tr>
<tr><td>IFAMP<td>0x2F2F</td><td>0x09</td><td>Intermediate Frequency Amplifier Configuration</td></tr>
<tr><td>LNA<td>0x2F30</td><td>0x01</td><td>Low Noise Amplifier Configuration</td></tr>
<tr><td>RXMIX<td>0x2F31</td><td>0x01</td><td>RX Mixer Configuration</td></tr>
<tr><td>XOSC5<td>0x2F32</td><td>0x0E</td><td>Crystal Oscillator Configuration Reg. 5</td></tr>
<tr><td>XOSC4<td>0x2F33</td><td>0xA0</td><td>Crystal Oscillator Configuration Reg. 4</td></tr>
<tr><td>XOSC3<td>0x2F34</td><td>0x03</td><td>Crystal Oscillator Configuration Reg. 3</td></tr>
<tr><td>XOSC2<td>0x2F35</td><td>0x04</td><td>Crystal Oscillator Configuration Reg. 2</td></tr>
<tr><td>XOSC1<td>0x2F36</td><td>0x03</td><td>Crystal Oscillator Configuration Reg. 1</td></tr>
<tr><td>XOSC0<td>0x2F37</td><td>0x00</td><td>Crystal Oscillator Configuration Reg. 0</td></tr>
<tr><td>ANALOG_SPARE<td>0x2F38</td><td>0x00</td><td>Analog Spare</td></tr>
<tr><td>PA_CFG3<td>0x2F39</td><td>0x00</td><td>Power Amplifier Configuration Reg. 3</td></tr>
<tr><td>WOR_TIME1<td>0x2F64</td><td>0x00</td><td>eWOR Timer Counter Value MSB</td></tr>
<tr><td>WOR_TIME0<td>0x2F65</td><td>0x00</td><td>eWOR Timer Counter Value LSB</td></tr>
<tr><td>WOR_CAPTURE1<td>0x2F66</td><td>0x00</td><td>eWOR Timer Capture Value MSB</td></tr>
<tr><td>WOR_CAPTURE0<td>0x2F67</td><td>0x00</td><td>eWOR Timer Capture Value LSB</td></tr>
<tr><td>BIST<td>0x2F68</td><td>0x00</td><td>MARC Built-In Self-Test</td></tr>
<tr><td>DCFILTOFFSET_I1<td>0x2F69</td><td>0x00</td><td>DC Filter Offset I MSB</td></tr>
<tr><td>DCFILTOFFSET_I0<td>0x2F6A</td><td>0x00</td><td>DC Filter Offset I LSB</td></tr>
<tr><td>DCFILTOFFSET_Q1<td>0x2F6B</td><td>0x00</td><td>DC Filter Offset Q MSB</td></tr>
<tr><td>DCFILTOFFSET_Q0<td>0x2F6C</td><td>0x00</td><td>DC Filter Offset Q LSB</td></tr>
<tr><td>IQIE_I1<td>0x2F6D</td><td>0x00</td><td>IQ Imbalance Value I MSB</td></tr>
<tr><td>IQIE_I0<td>0x2F6E</td><td>0x00</td><td>IQ Imbalance Value I LSB</td></tr>
<tr><td>IQIE_Q1<td>0x2F6F</td><td>0x00</td><td>IQ Imbalance Value Q MSB</td></tr>
<tr><td>IQIE_Q0<td>0x2F70</td><td>0x00</td><td>IQ Imbalance Value Q LSB</td></tr>
<tr><td>RSSI1<td>0x2F71</td><td>0x80</td><td>Received Signal Strength Indicator Reg. 1</td></tr>
<tr><td>RSSI0<td>0x2F72</td><td>0x00</td><td>Received Signal Strength Indicator Reg.0</td></tr>
<tr><td>MARCSTATE<td>0x2F73</td><td>0x41</td><td>MARC State</td></tr>
<tr><td>LQI_VAL<td>0x2F74</td><td>0x00</td><td>Link Quality Indicator Value</td></tr>
<tr><td>PQT_SYNC_ERR<td>0x2F75</td><td>0xFF</td><td>Preamble and Sync Word Error</td></tr>
<tr><td>DEM_STATUS<td>0x2F76</td><td>0x00</td><td>Demodulator Status</td></tr>
<tr><td>FREQOFF_EST1<td>0x2F77</td><td>0x00</td><td>Frequency Offset Estimate MSB</td></tr>
<tr><td>FREQOFF_EST0<td>0x2F78</td><td>0x00</td><td>Frequency Offset Estimate LSB</td></tr>
<tr><td>AGC_GAIN3<td>0x2F79</td><td>0x00</td><td>Automatic Gain Control Reg. 3</td></tr>
<tr><td>AGC_GAIN2<td>0x2F7A</td><td>0xD1</td><td>Automatic Gain Control Reg. 2</td></tr>
<tr><td>AGC_GAIN1<td>0x2F7B</td><td>0x00</td><td>Automatic Gain Control Reg. 1</td></tr>
<tr><td>AGC_GAIN0<td>0x2F7C</td><td>0x3F</td><td>Automatic Gain Control Reg. 0</td></tr>
<tr><td>CFM_RX_DATA_OUT<td>0x2F7D</td><td>0x00</td><td>Custom Frequency Modulation RX Data</td></tr>
<tr><td>CFM_TX_DATA_IN<td>0x2F7E</td><td>0x00</td><td>Custom Frequency Modulation TX Data</td></tr>
<tr><td>ASK_SOFT_RX_DATA<td>0x2F7F</td><td>0x30</td><td>ASK Soft Decision Output</td></tr>
<tr><td>RNDGEN<td>0x2F80</td><td>0x7F</td><td>Random Number Generator Value</td></tr>
<tr><td>MAGN2<td>0x2F81</td><td>0x00</td><td>Signal Magnitude after CORDIC [16]</td></tr>
<tr><td>MAGN1<td>0x2F82</td><td>0x00</td><td>Signal Magnitude after CORDIC [15:8]</td></tr>
<tr><td>MAGN0<td>0x2F83</td><td>0x00</td><td>Signal Magnitude after CORDIC [7:0]</td></tr>
<tr><td>ANG1<td>0x2F84</td><td>0x00</td><td>Signal Angular after CORDIC [9:8]</td></tr>
<tr><td>ANG0<td>0x2F85</td><td>0x00</td><td>Signal Angular after CORDIC [7:0]</td></tr>
<tr><td>CHFILT_I2<td>0x2F86</td><td>0x02</td><td>Channel Filter Data Real Part [16]</td></tr>
<tr><td>CHFILT_I1<td>0x2F87</td><td>0x00</td><td>Channel Filter Data Real Part [15:8]</td></tr>
<tr><td>CHFILT_I0<td>0x2F88</td><td>0x00</td><td>Channel Filter Data Real Part [7:0]</td></tr>
<tr><td>CHFILT_Q2<td>0x2F89</td><td>0x00</td><td>Channel Filter Data Imaginary Part [16]</td></tr>
<tr><td>CHFILT_Q1<td>0x2F8A</td><td>0x00</td><td>Channel Filter Data Imaginary Part [15:8]</td></tr>
<tr><td>CHFILT_Q0<td>0x2F8B</td><td>0x00</td><td>Channel Filter Data Imaginary Part [7:0]</td></tr>
<tr><td>GPIO_STATUS<td>0x2F8C</td><td>0x00</td><td>General Purpose Input/Output Status</td></tr>
<tr><td>FSCAL_CTRL<td>0x2F8D</td><td>0x01</td><td>Frequency Synthesizer Calibration Control</td></tr>
<tr><td>PHASE_ADJUST<td>0x2F8E</td><td>0x00</td><td>Frequency Synthesizer Phase Adjust</td></tr>
<tr><td>PARTNUMBER<td>0x2F8F</td><td>0x00</td><td>Part Number</td></tr>
<tr><td>PARTVERSION<td>0x2F90</td><td>0x00</td><td>Part Revision</td></tr>
<tr><td>SERIAL_STATUS<td>0x2F91</td><td>0x00</td><td>Serial Status</td></tr>
<tr><td>MODEM_STATUS1<td>0x2F92</td><td>0x01</td><td>Modem Status Reg. 1</td></tr>
<tr><td>MODEM_STATUS0<td>0x2F93</td><td>0x00</td><td>Modem Status Reg. 0</td></tr>
<tr><td>MARC_STATUS1<td>0x2F94</td><td>0x00</td><td>MARC Status Reg. 1</td></tr>
<tr><td>MARC_STATUS0<td>0x2F95</td><td>0x00</td><td>MARC Status Reg. 0</td></tr>
<tr><td>PA_IFAMP_TEST<td>0x2F96</td><td>0x00</td><td>Power Amplifier Intermediate Frequency Amplifier T..</td></tr>
<tr><td>FSRF_TEST<td>0x2F97</td><td>0x00</td><td>Frequency Synthesizer Test</td></tr>
<tr><td>PRE_TEST<td>0x2F98</td><td>0x00</td><td>Frequency Synthesizer Prescaler Test</td></tr>
<tr><td>PRE_OVR<td>0x2F99</td><td>0x00</td><td>Frequency Synthesizer Prescaler Override</td></tr>
<tr><td>ADC_TEST<td>0x2F9A</td><td>0x00</td><td>Analog to Digital Converter Test</td></tr>
<tr><td>DVC_TEST<td>0x2F9B</td><td>0x0B</td><td>Digital Divider Chain Test</td></tr>
<tr><td>ATEST<td>0x2F9C</td><td>0x40</td><td>Analog Test</td></tr>
<tr><td>ATEST_LVDS<td>0x2F9D</td><td>0x00</td><td>Analog Test LVDS</td></tr>
<tr><td>ATEST_MODE<td>0x2F9E</td><td>0x00</td><td>Analog Test Mode</td></tr>
<tr><td>XOSC_TEST1<td>0x2F9F</td><td>0x3C</td><td>Crystal Oscillator Test Reg. 1</td></tr>
<tr><td>XOSC_TEST0<td>0x2FA0</td><td>0x00</td><td>Crystal Oscillator Test Reg. 0</td></tr>
<tr><td>AES<td>0x2FA1</td><td>0x00</td><td>AES</td></tr>
<tr><td>MDM_TEST<td>0x2FA2</td><td>0x00</td><td>MODEM Test</td></tr>
<tr><td>RXFIRST<td>0x2FD2</td><td>0x00</td><td>RX FIFO Pointer First Entry</td></tr>
<tr><td>TXFIRST<td>0x2FD3</td><td>0x00</td><td>TX FIFO Pointer First Entry</td></tr>
<tr><td>RXLAST<td>0x2FD4</td><td>0x00</td><td>RX FIFO Pointer Last Entry</td></tr>
<tr><td>TXLAST<td>0x2FD5</td><td>0x00</td><td>TX FIFO Pointer Last Entry</td></tr>
<tr><td>NUM_TXBYTES<td>0x2FD6</td><td>0x00</td><td>TX FIFO Status</td></tr>
<tr><td>NUM_RXBYTES<td>0x2FD7</td><td>0x00</td><td>RX FIFO Status</td></tr>
<tr><td>FIFO_NUM_TXBYTES<td>0x2FD8</td><td>0x0F</td><td>TX FIFO Status</td></tr>
<tr><td>FIFO_NUM_RXBYTES<td>0x2FD9</td><td>0x00</td><td>RX FIFO Status</td></tr>
<tr><td>RXFIFO_PRE_BUF<td>0x2FDA</td><td>0x00</td><td>RX FIFO Status</td></tr>
<tr><td>AES_KEY15<td>0x2FE0</td><td>0x00</td><td>Advanced Encryption Standard Key [127:120]</td></tr>
<tr><td>AES_KEY14<td>0x2FE1</td><td>0x00</td><td>Advanced Encryption Standard Key [119:112]</td></tr>
<tr><td>AES_KEY13<td>0x2FE2</td><td>0x00</td><td>Advanced Encryption Standard Key [111:104]</td></tr>
<tr><td>AES_KEY12<td>0x2FE3</td><td>0x00</td><td>Advanced Encryption Standard Key [103:96]</td></tr>
<tr><td>AES_KEY11<td>0x2FE4</td><td>0x00</td><td>Advanced Encryption Standard Key [95:88]</td></tr>
<tr><td>AES_KEY10<td>0x2FE5</td><td>0x00</td><td>Advanced Encryption Standard Key [87:80]</td></tr>
<tr><td>AES_KEY9<td>0x2FE6</td><td>0x00</td><td>Advanced Encryption Standard Key [79:72]</td></tr>
<tr><td>AES_KEY8<td>0x2FE7</td><td>0x00</td><td>Advanced Encryption Standard Key [71:64]</td></tr>
<tr><td>AES_KEY7<td>0x2FE8</td><td>0x00</td><td>Advanced Encryption Standard Key [63:56]</td></tr>
<tr><td>AES_KEY6<td>0x2FE9</td><td>0x00</td><td>Advanced Encryption Standard Key [55:48]</td></tr>
<tr><td>AES_KEY5<td>0x2FEA</td><td>0x00</td><td>Advanced Encryption Standard Key [47:40]</td></tr>
<tr><td>AES_KEY4<td>0x2FEB</td><td>0x00</td><td>Advanced Encryption Standard Key [39:32]</td></tr>
<tr><td>AES_KEY3<td>0x2FEC</td><td>0x00</td><td>Advanced Encryption Standard Key [31:24]</td></tr>
<tr><td>AES_KEY2<td>0x2FED</td><td>0x00</td><td>Advanced Encryption Standard Key [23:16]</td></tr>
<tr><td>AES_KEY1<td>0x2FEE</td><td>0x00</td><td>Advanced Encryption Standard Key [15:8]</td></tr>
<tr><td>AES_KEY0<td>0x2FEF</td><td>0x00</td><td>Advanced Encryption Standard Key [7:0]</td></tr>
<tr><td>AES_BUFFER15<td>0x2FF0</td><td>0x00</td><td>Advanced Encryption Standard Buffer [127:120]</td></tr>
<tr><td>AES_BUFFER14<td>0x2FF1</td><td>0x00</td><td>Advanced Encryption Standard Buffer [119:112]</td></tr>
<tr><td>AES_BUFFER13<td>0x2FF2</td><td>0x00</td><td>Advanced Encryption Standard Buffer [111:104]</td></tr>
<tr><td>AES_BUFFER12<td>0x2FF3</td><td>0x00</td><td>Advanced Encryption Standard Buffer [103:93]</td></tr>
<tr><td>AES_BUFFER11<td>0x2FF4</td><td>0x00</td><td>Advanced Encryption Standard Buffer [95:88]</td></tr>
<tr><td>AES_BUFFER10<td>0x2FF5</td><td>0x00</td><td>Advanced Encryption Standard Buffer [87:80]</td></tr>
<tr><td>AES_BUFFER9<td>0x2FF6</td><td>0x00</td><td>Advanced Encryption Standard Buffer [79:72]</td></tr>
<tr><td>AES_BUFFER8<td>0x2FF7</td><td>0x00</td><td>Advanced Encryption Standard Buffer [71:64]</td></tr>
<tr><td>AES_BUFFER7<td>0x2FF8</td><td>0x00</td><td>Advanced Encryption Standard Buffer [63:56]</td></tr>
<tr><td>AES_BUFFER6<td>0x2FF9</td><td>0x00</td><td>Advanced Encryption Standard Buffer [55:48]</td></tr>
<tr><td>AES_BUFFER5<td>0x2FFA</td><td>0x00</td><td>Advanced Encryption Standard Buffer [47:40]</td></tr>
<tr><td>AES_BUFFER4<td>0x2FFB</td><td>0x00</td><td>Advanced Encryption Standard Buffer [39:32]</td></tr>
<tr><td>AES_BUFFER3<td>0x2FFC</td><td>0x00</td><td>Advanced Encryption Standard Buffer [31:24]</td></tr>
<tr><td>AES_BUFFER2<td>0x2FFD</td><td>0x00</td><td>Advanced Encryption Standard Buffer [23:16]</td></tr>
<tr><td>AES_BUFFER1<td>0x2FFE</td><td>0x00</td><td>Advanced Encryption Standard Buffer [15:8]</td></tr>
<tr><td>AES_BUFFER0<td>0x2FFF</td><td>0x00</td><td>Advanced Encryption Standard Buffer [7:0]</td></tr>
</table>
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