Other Parts Discussed in Thread: CC1101, CC2500, , CC1190
This has been an ongoing issue for us and it really needs to get resolved.
We have a custom CC1310-1190 board based on the reference design. Everything works fine at 2.5 kbps but we cannot
get it to work at 5 kbps.
I believe the most important clue is that if our board is being controlled by RF studio it works fine at 5 kbps. With our own
software it does not. I have verified that all the settings between RF studio and our software match. This leads me to
believe there is a configuration setting that's different between RF Studio and our software. Since there is no way to
read registers in RF Studio I can't perform a complete comparison of other CPU registers.
Here's what we have checked so far:
- 32.768 KHz clock looks fine
- All RF Studio-generated settings match
- Our software running on the Launchpad does not work
- Modified XOSC_CAPARRAY_DELTA in 1 pF increments from 2.1 pF to 11.1 pF and nothing changed
- We are using the RF Studio default settings for 5 kbps except we're running at 915 MHz and have IEEE whitener enabled.
I have attached the RF config files we are using.
Does anyone have any ideas?
Victor
smartrf_settings_2_5_kbps_1190.c
//*********************************************************************************
// Generated by SmartRF Studio version 2.8.0 ( build #41)
// Compatible with SimpleLink SDK version: CC13x0 SDK 1.60.xx.xx
// Device: CC1310 Rev. 2.1 (Rev. B)
//
//*********************************************************************************
//*********************************************************************************
// Parameter summary
// Address: off
// Address0: 0xAA
// Address1: 0xBB
// Frequency: 915.00000 MHz
// Data Format: Serial mode disable
// Deviation: 5.000 kHz
// pktLen: 30
// 802.15.4g Mode: off
// Select bit order to transmit PSDU octets:: 1
// Packet Length Config: Variable
// Max Packet Length: 128
// Packet Length: 20
// RX Filter BW: 49 kHz
// Symbol Rate: 19.99969 kBaud
// Sync Word Length: 32 Bits
// TX Power: 26 dBm (requires define CCFG_FORCE_VDDR_HH = 0 in ccfg.c, see CC13xx/CC26xx Technical Reference Manual)
// Whitening: IEEE 802.15.4g compatible whitener and 32-bit CRC
#include <ti/devices/DeviceFamily.h>
#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h)
#include <ti/drivers/rf/RF.h>
#include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_sl_longrange.h)
#include DeviceFamily_constructPath(rf_patches/rf_patch_rfe_sl_longrange.h)
#include DeviceFamily_constructPath(rf_patches/rf_patch_mce_sl_longrange.h)
#include "smartrf_settings_2_5_kbps_1190.h"
// TI-RTOS RF Mode Object
RF_Mode RF_prop =
{
.rfMode = RF_MODE_PROPRIETARY_SUB_1,
.cpePatchFxn = &rf_patch_cpe_sl_longrange,
.mcePatchFxn = &rf_patch_mce_sl_longrange,
.rfePatchFxn = &rf_patch_rfe_sl_longrange,
};
// Overrides for CMD_PROP_RADIO_DIV_SETUP
uint32_t pOverrides[] =
{
// override_use_patch_simplelink_long_range.xml
// PHY: Use MCE RAM patch, RFE RAM patch
MCE_RFE_OVERRIDE(1,0,0,1,0,0),
// override_synth_prop_863_930_div5_lbw60k.xml
// Synth: Set recommended RTRIM to 7
HW_REG_OVERRIDE(0x4038,0x0037),
// Synth: Set Fref to 4 MHz
(uint32_t)0x000684A3,
// Synth: Configure fine calibration setting
HW_REG_OVERRIDE(0x4020,0x7F00),
// Synth: Configure fine calibration setting
HW_REG_OVERRIDE(0x4064,0x0040),
// Synth: Configure fine calibration setting
(uint32_t)0xB1070503,
// Synth: Configure fine calibration setting
(uint32_t)0x05330523,
// Synth: Set loop bandwidth after lock to 60 kHz
(uint32_t)0x40410583,
// Synth: Set loop bandwidth after lock to 60 kHz
(uint32_t)0x32CC0603,
// Synth: Set loop bandwidth after lock to 60 kHz
(uint32_t)0x00010623,
// Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
ADI_REG_OVERRIDE(1,4,0x9F),
// Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1)
ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
// Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering
(uint32_t)0x02010403,
// Synth: Configure extra PLL filtering
(uint32_t)0x00108463,
// Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us)
(uint32_t)0x04B00243,
// override_synth_disable_bias_div5.xml
// Synth: Set divider bias to disabled
HW32_ARRAY_OVERRIDE(0x405C,1),
// Synth: Set divider bias to disabled (specific for loDivider=5)
(uint32_t)0x18000200,
// override_phy_rx_aaf_bw_0xd.xml
// Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
// override_phy_gfsk_rx.xml
// Rx: Set LNA bias current trim offset to 3
(uint32_t)0x00038883,
// Rx: Freeze RSSI on sync found event
HW_REG_OVERRIDE(0x6084,0x35F1),
// override_phy_gfsk_pa_ramp_agc_reflevel_0x14.xml
// Tx: Configure PA ramping setting (0x41). Rx: Set AGC reference level to 0x14.
HW_REG_OVERRIDE(0x6088,0x4114),
// Tx: Configure PA ramping setting
HW_REG_OVERRIDE(0x608C,0x8213),
// override_phy_long_range_dsss4.xml
// PHY: Configure DSSS SF=4
HW_REG_OVERRIDE(0x505C,0x0303),
// override_phy_rx_rssi_offset_cc1310_cc1190_9092.xml
// Rx: Set RSSI offset to adjust reported RSSI by +26 dB
(uint32_t)0x000388A3,
(uint32_t)0xFFFFFFFF,
};
// CMD_PROP_RADIO_DIV_SETUP
// Proprietary Mode Radio Setup Command for All Frequency Bands
rfc_CMD_PROP_RADIO_DIV_SETUP_t RF_cmdPropRadioDivSetup =
{
.commandNo = 0x3807,
.status = 0x0000,
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.modulation.modType = 0x1,
.modulation.deviation = 0x14,
.symbolRate.preScale = 0xF,
.symbolRate.rateWord = 0x3333,
.rxBw = 0x21,
.preamConf.nPreamBytes = 0x2,
.preamConf.preamMode = 0x0,
.formatConf.nSwBits = 0x20,
.formatConf.bBitReversal = 0x0,
.formatConf.bMsbFirst = 0x0,
.formatConf.fecMode = 0x8,
.formatConf.whitenMode = 0x5,
.config.frontEndMode = 0x0,
.config.biasMode = 0x1,
.config.analogCfgMode = 0x0,
.config.bNoFsPowerUp = 0x0,
.txPower = 0x00CE,
.pRegOverride = pOverrides,
.centerFreq = 0x0393,
.intFreq = 0x8000,
.loDivider = 0x05,
};
// CMD_FS
// Frequency Synthesizer Programming Command
rfc_CMD_FS_t RF_cmdFs =
{
.commandNo = 0x0803,
.status = 0x0000,
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.frequency = 0x0393,
.fractFreq = 0x0000,
.synthConf.bTxMode = 0x0,
.synthConf.refFreq = 0x0,
.__dummy0 = 0x00,
.__dummy1 = 0x00,
.__dummy2 = 0x00,
.__dummy3 = 0x0000,
};
// CMD_PROP_TX
// Proprietary Mode Transmit Command
rfc_CMD_PROP_TX_t RF_cmdPropTx =
{
.commandNo = 0x3801,
.status = 0x0000,
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.pktConf.bFsOff = 0x0,
.pktConf.bUseCrc = 0x1,
.pktConf.bVarLen = 0x1,
.pktLen = 0x14,
.syncWord = 0x930B51DE,
.pPkt = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
};
// CMD_PROP_RX
// Proprietary Mode Receive Command
rfc_CMD_PROP_RX_t RF_cmdPropRx =
{
.commandNo = 0x3802,
.status = 0x0000,
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.pktConf.bFsOff = 0x0,
.pktConf.bRepeatOk = 0x0,
.pktConf.bRepeatNok = 0x0,
.pktConf.bUseCrc = 0x1,
.pktConf.bVarLen = 0x1,
.pktConf.bChkAddress = 0x0,
.pktConf.endType = 0x0,
.pktConf.filterOp = 0x0,
.rxConf.bAutoFlushIgnored = 0x0,
.rxConf.bAutoFlushCrcErr = 0x0,
.rxConf.bIncludeHdr = 0x1,
.rxConf.bIncludeCrc = 0x0,
.rxConf.bAppendRssi = 0x0,
.rxConf.bAppendTimestamp = 0x0,
.rxConf.bAppendStatus = 0x1,
.syncWord = 0x930B51DE,
.maxPktLen = 0x80,
.address0 = 0xAA,
.address1 = 0xBB,
.endTrigger.triggerType = 0x1,
.endTrigger.bEnaCmd = 0x0,
.endTrigger.triggerNo = 0x0,
.endTrigger.pastTrig = 0x0,
.endTime = 0x00000000,
.pQueue = 0, // INSERT APPLICABLE POINTER: (dataQueue_t*)&xxx
.pOutput = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
};
3157.smartrf_settings_5_0_kbps_1190.c
//*********************************************************************************
// Generated by SmartRF Studio version 2.9.0 (build#85)
// Compatible with SimpleLink SDK version: CC13x0 SDK 2.10.xx.xx
// Device: CC1310 Rev. 2.1 (Rev. B)
//
//*********************************************************************************
//*********************************************************************************
// Parameter summary
// Address: 0
// Address0: 0xAA
// Address1: 0xBB
// Frequency: 915.00000 MHz
// Data Format: Serial mode disable
// Deviation: 5.000 kHz
// pktLen: 30
// 802.15.4g Mode: 0
// Select bit order to transmit PSDU octets:: 1
// Packet Length Config: Variable
// Max Packet Length: 128
// Packet Length: 20
// Packet Data: 255
// RX Filter BW: 49 kHz
// Symbol Rate: 19.99969 kBaud
// Sync Word Length: 32 Bits
// TX Power: 26 dBm (requires define CCFG_FORCE_VDDR_HH = 0 in ccfg.c, see CC13xx/CC26xx Technical Reference Manual)
// Whitening: No whitening
#include <ti/devices/DeviceFamily.h>
#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h)
#include <ti/drivers/rf/RF.h>
#include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_sl_longrange.h)
#include DeviceFamily_constructPath(rf_patches/rf_patch_rfe_sl_longrange.h)
#include DeviceFamily_constructPath(rf_patches/rf_patch_mce_sl_longrange.h)
#include "smartrf_settings_5_0_kbps_1190.h"
// TI-RTOS RF Mode Object
RF_Mode RF_prop =
{
.rfMode = RF_MODE_PROPRIETARY_SUB_1,
.cpePatchFxn = &rf_patch_cpe_sl_longrange,
.mcePatchFxn = &rf_patch_mce_sl_longrange,
.rfePatchFxn = &rf_patch_rfe_sl_longrange,
};
// TX Power table
// The RF_TxPowerTable_DEFAULT_PA_ENTRY macro is defined in RF.h and requires the following arguments:
// RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost coefficient)
// See the Technical Reference Manual for further details about the "txPower" Command field.
// The PA settings require the CCFG_FORCE_VDDR_HH = 0 unless stated otherwise.
RF_TxPowerTable_Entry txPowerTable[] =
{
{7, RF_TxPowerTable_DEFAULT_PA_ENTRY(0, 3, 0, 0) },
{14, RF_TxPowerTable_DEFAULT_PA_ENTRY(1, 3, 0, 0) },
{18, RF_TxPowerTable_DEFAULT_PA_ENTRY(2, 3, 0, 0) },
{20, RF_TxPowerTable_DEFAULT_PA_ENTRY(3, 3, 0, 0) },
{22, RF_TxPowerTable_DEFAULT_PA_ENTRY(4, 3, 0, 0) },
{23, RF_TxPowerTable_DEFAULT_PA_ENTRY(5, 3, 0, 0) },
{24, RF_TxPowerTable_DEFAULT_PA_ENTRY(6, 3, 0, 0) },
{25, RF_TxPowerTable_DEFAULT_PA_ENTRY(9, 3, 0, 0) },
{26, RF_TxPowerTable_DEFAULT_PA_ENTRY(14, 3, 0, 0) },
RF_TxPowerTable_TERMINATION_ENTRY
};
// Overrides for CMD_PROP_RADIO_DIV_SETUP
uint32_t pOverrides[] =
{
// override_use_patch_simplelink_long_range.xml
// PHY: Use MCE RAM patch, RFE RAM patch
MCE_RFE_OVERRIDE(1,0,0,1,0,0),
// override_synth_prop_863_930_div5_lbw60k.xml
// Synth: Set recommended RTRIM to 7
HW_REG_OVERRIDE(0x4038,0x0037),
// Synth: Set Fref to 4 MHz
(uint32_t)0x000684A3,
// Synth: Configure fine calibration setting
HW_REG_OVERRIDE(0x4020,0x7F00),
// Synth: Configure fine calibration setting
HW_REG_OVERRIDE(0x4064,0x0040),
// Synth: Configure fine calibration setting
(uint32_t)0xB1070503,
// Synth: Configure fine calibration setting
(uint32_t)0x05330523,
// Synth: Set loop bandwidth after lock to 60 kHz
(uint32_t)0x40410583,
// Synth: Set loop bandwidth after lock to 60 kHz
(uint32_t)0x32CC0603,
// Synth: Set loop bandwidth after lock to 60 kHz
(uint32_t)0x00010623,
// Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
ADI_REG_OVERRIDE(1,4,0x9F),
// Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1)
ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
// Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering
(uint32_t)0x02010403,
// Synth: Configure extra PLL filtering
(uint32_t)0x00108463,
// Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us)
(uint32_t)0x04B00243,
// override_synth_disable_bias_div5.xml
// Synth: Set divider bias to disabled
HW32_ARRAY_OVERRIDE(0x405C,1),
// Synth: Set divider bias to disabled (specific for loDivider=5)
(uint32_t)0x18000200,
// override_phy_rx_aaf_bw_0xd.xml
// Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
// override_phy_gfsk_rx.xml
// Rx: Set LNA bias current trim offset to 3
(uint32_t)0x00038883,
// Rx: Freeze RSSI on sync found event
HW_REG_OVERRIDE(0x6084,0x35F1),
// override_phy_gfsk_pa_ramp_agc_reflevel_0x14.xml
// Tx: Configure PA ramping setting (0x41). Rx: Set AGC reference level to 0x14.
HW_REG_OVERRIDE(0x6088,0x4114),
// Tx: Configure PA ramping setting
HW_REG_OVERRIDE(0x608C,0x8213),
// override_phy_long_range_dsss2.xml
// PHY: Configure DSSS SF=2
HW_REG_OVERRIDE(0x505C,0x0100),
// override_phy_rx_rssi_offset_cc1310_cc1190_9092.xml
// Rx: Set RSSI offset to adjust reported RSSI by +26 dB
(uint32_t)0x000388A3,
(uint32_t)0xFFFFFFFF,
};
// CMD_PROP_RADIO_DIV_SETUP
// Proprietary Mode Radio Setup Command for All Frequency Bands
rfc_CMD_PROP_RADIO_DIV_SETUP_t RF_cmdPropRadioDivSetup =
{
.commandNo = 0x3807,
.status = 0x0000,
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.modulation.modType = 0x1,
.modulation.deviation = 0x14,
.symbolRate.preScale = 0xF,
.symbolRate.rateWord = 0x3333,
.rxBw = 0x21,
.preamConf.nPreamBytes = 0x2,
.preamConf.preamMode = 0x0,
.formatConf.nSwBits = 0x20,
.formatConf.bBitReversal = 0x0,
.formatConf.bMsbFirst = 0x0,
.formatConf.fecMode = 0x8,
.formatConf.whitenMode = 0x0,
.config.frontEndMode = 0x0,
.config.biasMode = 0x1,
.config.analogCfgMode = 0x0,
.config.bNoFsPowerUp = 0x0,
.txPower = 0x00CE,
.pRegOverride = pOverrides,
.centerFreq = 0x0393,
.intFreq = 0x8000,
.loDivider = 0x05,
};
// CMD_FS
// Frequency Synthesizer Programming Command
rfc_CMD_FS_t RF_cmdFs =
{
.commandNo = 0x0803,
.status = 0x0000,
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.frequency = 0x0393,
.fractFreq = 0x0000,
.synthConf.bTxMode = 0x0,
.synthConf.refFreq = 0x0,
.__dummy0 = 0x00,
.__dummy1 = 0x00,
.__dummy2 = 0x00,
.__dummy3 = 0x0000,
};
// CMD_PROP_RX
// Proprietary Mode Receive Command
rfc_CMD_PROP_RX_t RF_cmdPropRx =
{
.commandNo = 0x3802,
.status = 0x0000,
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.pktConf.bFsOff = 0x0,
.pktConf.bRepeatOk = 0x0,
.pktConf.bRepeatNok = 0x0,
.pktConf.bUseCrc = 0x1,
.pktConf.bVarLen = 0x1,
.pktConf.bChkAddress = 0x0,
.pktConf.endType = 0x0,
.pktConf.filterOp = 0x0,
.rxConf.bAutoFlushIgnored = 0x0,
.rxConf.bAutoFlushCrcErr = 0x0,
.rxConf.bIncludeHdr = 0x1,
.rxConf.bIncludeCrc = 0x0,
.rxConf.bAppendRssi = 0x0,
.rxConf.bAppendTimestamp = 0x0,
.rxConf.bAppendStatus = 0x1,
.syncWord = 0x930B51DE,
.maxPktLen = 0x80,
.address0 = 0xAA,
.address1 = 0xBB,
.endTrigger.triggerType = 0x1,
.endTrigger.bEnaCmd = 0x0,
.endTrigger.triggerNo = 0x0,
.endTrigger.pastTrig = 0x0,
.endTime = 0x00000000,
.pQueue = 0, // INSERT APPLICABLE POINTER: (dataQueue_t*)&xxx
.pOutput = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
};
// CMD_PROP_TX
// Proprietary Mode Transmit Command
rfc_CMD_PROP_TX_t RF_cmdPropTx =
{
.commandNo = 0x3801,
.status = 0x0000,
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.pktConf.bFsOff = 0x0,
.pktConf.bUseCrc = 0x1,
.pktConf.bVarLen = 0x1,
.pktLen = 0x14,
.syncWord = 0x930B51DE,
.pPkt = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
};
