CC1200: When is PKT_CRC_OK in the LQI_VAL register updated?

Hi

The device is used with PKT_CFG1 = 0x03 and Data field = 4Byte.
When is PKT_CRC_OK reflected in the LQI_VAL register?

You should not check the PKT_CRC_OK bit in the LQI_VAL register before you have gotten the packet received indication (falling edge of PKT_SYNC_RXTX). Note that this signal will also be de-asserted if a packet is discarded due to any kind of packet filtering, so you should check that there are data in the RXFIFO before checking the CRC. If CRC OK, you can read out the data, if CRC is not OK, you can flush the RX FIFO.

When is the timing when the MARCSTATUS register becomes RX_END?

We do not have info on this, but most likely you will not be able to read that MARCSTATE is in this state, as this is only an intermediate state before it device determines if it should go back to RX or if it should go to IDLE.

What is the relationship between the MARCSTATUS register RX_END and FIFO_CFG.FIFO_THR?

There are no relations between RX_END and FIFO_CFG.FIFO_THR

How does FIFO_THR affect TX FIFO or transmission?

How the FIFO_THR works is explained in Section 8.6 in the User Guide.

The FIFO_THR affect how the 4 FIFO signals (IOCFGx = 0, 1, 2or 3) behaves. These signals are only necessary to use in the cases where you your packets are larger than the FIFO and you need to write the TX FIFO or read the RX FIFO several times during active RX or TX mode.

What should the value of FIFO_THR be set in this case?

Not sure what you mean by “this case”

Have you looked at the available code examples on how to transit and receive packets? They would be a good starting point:

BR

Siri

Hi

I am a bit unsure why you are doing the steps you are doing in your code.

First of all, FIFO_CFG_FIFO_THR is not related to the updating of the LQI_VAL register, and as far as I can see from your code, you do not use it for anything.

You should not wait for RX_END or IDLE. This is not the same. RX_END is when the radio is done receive data on the air. The chip will be a short time in this state when it calculates CRC, add appended status bytes etc., before it move to IDLE. You should wait for IDLE always.

I did a test where I checked the LQI_VAL register. I tested both with FIFO_CFG_FIFO_THR = 4 and FIFO_CFG_FIFO_THR = 6, and I tested with either waiting for falling edge on PKT_SYNC_RXTX or by waiting for IDLE. I always sent a packet with 4 bytes payload after sync (including length byte).

My test cases are below.

    //--------------------------------------------------------------------------
    // FIFO_CFG = 4 and wait for PKT_SYNC_RXTX
    writeByte = 0x04;
    cc120xSpiWriteReg(CC120X_FIFO_CFG, &writeByte, 1);

    trxSpiCmdStrobe(CC120X_SRX);
    
    // Wait for falling edge on PKT_SYNC_RXTX
    while(packetSemaphore != ISR_ACTION_REQUIRED); 
    
    cc120xSpiReadRxFifo(rxBuffer, 4);
    
    cc120xSpiReadReg(CC120X_LQI_VAL, &lqi_val, 1);
    //--------------------------------------------------------------------------
    

    //--------------------------------------------------------------------------
    // FIFO_CFG = 6 and wait for PKT_SYNC_RXTX
    writeByte = 0x06;
    cc120xSpiWriteReg(CC120X_FIFO_CFG, &writeByte, 1);

    trxSpiCmdStrobe(CC120X_SRX);
    
    // Wait for falling edge on PKT_SYNC_RXTX
    while(packetSemaphore != ISR_ACTION_REQUIRED); 
    
    cc120xSpiReadRxFifo(rxBuffer, 4);
    
    cc120xSpiReadReg(CC120X_LQI_VAL, &lqi_val, 1);
    //--------------------------------------------------------------------------
    

    //--------------------------------------------------------------------------
    // FIFO_CFG = 4 and wait for IDLE
    writeByte = 0x04;
    cc120xSpiWriteReg(CC120X_FIFO_CFG, &writeByte, 1);

    trxSpiCmdStrobe(CC120X_SRX);
    
    // Wait for Radio to be back in IDLE
    do {
      cc120xSpiReadReg(CC120X_MARCSTATE, &marcstate, 1);
    } while (marcstate != 0x41);

    cc120xSpiReadRxFifo(rxBuffer, 4);
    
    cc120xSpiReadReg(CC120X_LQI_VAL, &lqi_val, 1);
    //--------------------------------------------------------------------------
    

    //--------------------------------------------------------------------------
    // FIFO_CFG = 6 and wait for IDLE
    writeByte = 0x06;
    cc120xSpiWriteReg(CC120X_FIFO_CFG, &writeByte, 1);

    trxSpiCmdStrobe(CC120X_SRX);
    
    // Wait for Radio to be back in IDLE
    do {
      cc120xSpiReadReg(CC120X_MARCSTATE, &marcstate, 1);
    } while (marcstate != 0x41);

    cc120xSpiReadRxFifo(rxBuffer, 4);
    
    cc120xSpiReadReg(CC120X_LQI_VAL, &lqi_val, 1);
    //--------------------------------------------------------------------------

BR

Siri