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CC1350: Recharge parameters in deep sleep

Paal Oeyvind Reichelt
Prodigy 152 points
Part Number: CC1350

I ran into an issue where it seems that VDDR regulation seems to go unstable during deep sleep. Here is the sequence of events and my theory of what goes wrong: 

  • CC1350 is run intermittently, and going into deep sleep with all power domains powered off for several hundred ms between each wakeup
    • After returning to active operation, SysCtrlAdjustRechargeAfterPowerDown(0); is called, so no margin on the recharge margin adjustment
  • Then, an event occurs and we change the SSI1 configuration and toggle a few bits before going back to deep sleep. To avoid resetting SSI1 upon returning from deep sleep, this time we don't power down the PERIPH domain so we retain the state.
  • When we go to deep sleep, the VDDR voltage dips dramatically (down to 0.7 V) and the VDDR regulator seems to struggle to regain control. The system behaves erratic after this.

I believe that the increased current consumption combined with no recharge margin adjustment makes the regulator fail. (Is this a likely hypothesis?) The regulator is also run with a capacitor that is lower than the recommendation from the reference design, likely adding to the issue. 

To solve this, I'd like to reset the recharge parameters to something with a low period so it adjusts to the higher current, so I do: 

SysCtrlSetRechargeBeforePowerDown(XOSC_IN_HIGH_POWER_MODE);
HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGECFG ) =
  ( 0x80A4E700 ) |
  ( 1 << AON_WUC_RECHARGECFG_PER_M_S );

to reset the recharge period to roughly 1ms (heavily inspired by SysCtrlSetRechargeBeforePowerDown in sys_ctrl.c).

This seems to work well. When the deep sleep cycle starts, the regulator starts out with a low recharge interval and then adjusts it up until a reasonable sawtooth amplitude is reached at VDDR.

My question is, is this a reasonable way to deal with it or do you have other suggested solutions that would be preferable?

  • 0
    TI__Guru**** 317180 points

    To see if I understand how you have implement things:

     - You go down in standby for close to a second which means that the recharge pulses have started to be a few hundred apart. 

    - When you wake up, and go down to standby you retain the current recharge pulse interval meaning that after you go down to standby the first recharge pulse comes after  a few hundred ms.

    - Then to save time you then keep a power domain on in standby meaning that the current draw in this state goes from very low to 100 uA ++?  

    If my understanding is correct I'm not surprised that VDDR drops to undefined levels since the "new" current draw would require frequent recharge pulses to keep VDDR within "legal" region. I addition when you use a smaller bulk cap on DCDC_SW than in the ref design you would need recharge pulses more often compared to the ref design. 

    I believe your suggested method sounds good since the user has limited ways to impact the recharge algorithm. Setting the initial interval is more or less the only option. So yes, ensuring that the initial recharge interval is small enough to ensure that the VDD does not drop below the threshold sounds like reasonable solution.  

  • 0 in reply to TER
    Prodigy 152 points

    Yeah your understanding is in line with mine, except the reasoning to keep the power domain on in this case is to ensure that we don't need to reinitialize the SSI (which would cost flash space and more importantly cause critical disruption to the state of the SPI lines).

    Anyway, thanks for the input!