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CC1352P: SmartRF Studio cannot open Device Control Panel

Part Number: CC1352P
Other Parts Discussed in Thread: SYSCONFIG

Hi team,

On customer's PCB, CC1352P is connected with another MCU (the CC1352P RESET_N is connected with one GPIO of the MCU). On their manufacturing line, they use SmartRF Studio to test RF performance. They find out if CC1352P is pre-programed with FW image, when launching SmartRF Studio, it will show "Not able to open Device Control". The fail rate is 80%. However, after doing "Forced Mass Erase", the SmartRF Studio can 100% connect the CC1352P.  

The want to clarify why CC1352P with pre-programmed FW image cause SmartRF Studio cannot work. 

Below show the scope measurement for RESET_N pin. For both OK case(first picture) & NG case(2nd picture), the RESET_N is pulled low (lower than 0.66V,  0.2*VDDS) for over 1us. It meets CC1352P data sheet spec.

Fig. 1, OK case:

Fig 2. NG case:

  • Hi Jerry,

    Did they add any write protect or similar?

  • Hi Marie,

    If the FW disable DEBUG on CCFG, the fail rate should be 100%, right ?

    Do you mean the below two in red ?

    @ccfg.c

    //#####################################
    // Debug access settings
    //#####################################

    #ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE
    #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option.
    // #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code
    #endif

    #ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE
    #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled
    //#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
    #endif

    #ifndef SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE
    #define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0x00 // Access disabled
    //#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
    #endif

    #ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE
    #define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled
    //#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
    #endif

    #ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE
    #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled
    // #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
    #endif

    #ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE
    #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled
    // #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
    #endif

    #ifndef SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE
    #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0x00 // Access disabled
    // #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
    #endif

     

  • Hi Jerry, 

    Which FW image are they using? Is it from the SDK?

    Which version of SmartRF Studio are they using?

    I have tested with the simple_peripheral_app.hex file from the CC13x2/CC26x2 3.40 SDK with SmartRF Studio versions 2.18.0 and 2.19.0 and I don't have a problem with opening the device control panel in any of the modes. 

    Thanks, 
    Elin

  • hi Elin,

    Which FW image are they using? Is it from the SDK?

    ==>Customer base on SDK and modify for their use-case.

    Which version of SmartRF Studio are they using?

    ==> 2.19.0

    I don't have a problem with opening the device control panel in any of the modes. 

    ==>what do you mean "in any of the modes" ? 

  • Hi Jerry, 

    Which example did they use? Can you provide the minimum code changes required to reproduce this issue?

    By modes I mean Proprietary mode, BLE mode, and IEEE 802.15.4 mode as you are prompted to select when trying to open the device control panel, aka double-clicking the device you want to work with. 

    Thanks,
    Elin

  • Hi Elin,

    I need to ask customer about code snippet.

    I did one test. If I use  SysConfig to disable JTAG access (disable option for "CPU DAP", "PWRPROF TAP") and flash image to CC1352P. Then SmartRF Studio cannot connect CC1352P. Is this correct ? 

    For customer's scenario, the fail rate is 80%. So, it doesn't relate to DEBUG access setting on CCFG, right ?

    We suggest customer to remove the connection between the CC1352P RESET_N pin and the GPIO of the MCU, then their problem is gone.

    Customer want to clarify what's the possible root cause make the fail rate for 80% ?  From the scope measurement, there is big difference on OK and NG case.

  • Hi Jerry,

    Correct, SmartRF Studio is using JTAG to connect to the chip. So if you remove the JTAG access, SmartRF Studio will not be able to connect to the chip.

    I think we can safely assume that it's not related to the debug access if by that you mean the JTAG access.

    I don't see any activity on the RESET_N pin when starting up SmartRF Studio and opening a device control panel. What did you do with the chip when performing the measurements in your original post and did you use a LaunchPad or a custom board?

    Jerry Kuo said:
    We suggest customer to remove the connection between the CC1352P RESET_N pin and the GPIO of the MCU, then their problem is gone.

    Okay so they have tested to remove the connection and that solved the problem? How did they remove the connection?

    Thanks, 
    Elin