• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 54 subscribers
  • Views 208 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CC1200: ADC data output thru SPI

Danilo A.
Mastermind 24705 points
Part Number: CC1200

Hi Team,

The block diagram of the CC1200 shows that the RX line-up starts with an LNA , the mixers, IF amplifiers, LPF then the 90dB dynamic range ADC. Is the ADC data output can be available from SPI port or by any other way. Can we configure the device to make this data available?

Regards,

Danilo

  • 0
    TI__Guru**** 317180 points

    For what usecase?

    It is possible to output the data from one ADC (not both) on a LVDS interface but that require a FPGA or similar clocked on 300 - 400 MHz to give enough oversampling.

  • 0 in reply to TER
    TI__Genius 10506 points

    Hi TER,

    I'm looped in on this request.  Thank you Danilo.  The customer wants to look at the ADC output to monitor for ADC saturation when an interferer is applied.  It's test purposes.

    How would they go about configuring the CC1200 to output the ADC to an LVDS output?

    Thanks,
    Darren

  • 0 in reply to Darren Jenkins
    TI__Guru**** 317180 points

    I have to dig some to find the required register settings. 

    But: This would require them to make some FW for a FPGA that process the LVDS data. 

    I don't fully understand the background for the question. Why do they want to look at the output spectrum with regards to blocking? Could you elaborate a bit on why they request this?   

  • 0 in reply to TER
    TI__Genius 10506 points

    Hi TER,

    They want to do this test so they can improve immunity to RF blocking.  When the ADC is saturated, they want to adjust the LNA and IF gain down until they are at minimum gain, and they want to find the limit under different conditions.  They have another test they want to do with the ADC data as well, and I better email that one to you if you're interested.

    Thanks,

    Darren

      

  • 0 in reply to Darren Jenkins
    TI__Guru**** 317180 points

    Please send a mail. 

    Also please ask them to read out AGC_GAIN3 which gives the front end gain. I believe that the gain is set to minimum long before the ADC goes into saturation. Or to put it differently, when the ADC is in saturation it's not possible to reduce the frontend gain further.