I'm trying to use the uDMA with I2C peripheral running as SLAVE and getting again issues with signal handling of the CPU.
The DMA is setup to transfer 40 bytes from a buffer to the FIFODATA register (or vice verse when i2c master writes data to cc3235 "slave").
Both I2C_SLAVE_INT_TX_DMA_DONE and I2C_SLAVE_INT_RX_DMA_DONE interrupts are enabled.
The problem occurs when the I2C master tries to read the CC3235.
1) I setup the DMA to transfer 40 bytes to the FIFO.
2) Then set a GPIO low.
3) The GPIO goes high when the I2C_SLAVE_INT_TX_DMA_DONE is done (GPIO signals internal semaphore when another transfer could occur).
The issue is: it seems that DMA TX DONE is signaled prematurely and causes the application to rewind/init the DMA and send the next buffer data overwriting/corrupting the transferred bytes.
In this image the overwrite occurs when the DMA_RDY signal goes high -> app reloads the DMA that points to a different buffer -> corrupts the ongoing I2C TX with filling the wrong data to FIFO.
Is there a method to signal the I2C transfer finished in any reliable way?
(Im not looking for a driver support i know the dirvers do not support this usecase, im interested in CPU/low level usage as per the swru543a Technical Reference Manual states that the CPU is equipped with I2C slave and uDMA)