We are designing a platform that takes many low latency data streams and multiplexes them into a single stream on the host side and sends them to many nodes that selects their data out of the stream for delivery.
We believe that doing this on the host side will add latency that we cannot work with and would like to configure and control via an FPGA and not have a microprocessor.
So, what I am really looking for is a document with a register map of the CC3300 and a flowchart or process map that shows the correct sequence to control the CC3300.
So, what I am really looking for is a document with a register map of the CC3300 and a flowchart or process map that shows the correct sequence to control the CC3300.
Best
Rob
