This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CC3300: CC3300 register access

Part Number: CC3300
We are designing a platform that takes many low latency data streams and multiplexes them into a single stream on the host side and sends them to many nodes that selects their data out of the stream for delivery.  
We believe that doing this on the host side will add latency that we cannot work with and would like to configure and control via an FPGA and not have a microprocessor.  

So, what I am really looking for is a document with a register map of the CC3300 and a flowchart or process map that shows the correct sequence to control the CC3300.
Best
Rob


  • Hi Robert,

    The CC3300's register map is restricted for external use.
    However, if you can elaborate on what you are trying to control on the CC3300 I might be able to assist you.

    Regards,

    Omri

  • Hi Rob,

    I think you are try to do what is not technically possible. Control WiFi device including TCP/IP from pure FPGA look like a sci-fi. May-by if you select FPGA+ARM like Zynq...

    Jan