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Part Number: CC3220SF-LAUNCHXL
Tool/software: Code Composer Studio
I am getting the same poor results found by Alexander at https://e2e.ti.com/support/wireless_connectivity/simplelink_wifi_cc31xx_cc32xx/f/968/t/629041. Ben Moore (TI) promised an internal review and updated documentation.
What is the status of this?
If it turns out that internal XIP flash on I-code/D-code is even worse than executing from external SRAM on sys bus, this is an embarrassing stumble by TI, and I regret to express my disappointment.
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In reply to Vincent Rodriguez:
In reply to cameron pike:
In reply to Alexander Podshivalov:
I spent some time this morning looking at this file, and others, sifting through documentation, and poking around with the debugger, but I was unable to find sufficient information to make any progress -- I would just be shooting in the dark.
Vincent, or Benjamin if you're watching, will you please procure an answer to our request? This matter is really quite important.
I am attaching a CCSv7 project which is a port of Coremark for cc3220SF. If any of you are able to repeat my results, please post on this thread.
coremark_v1.0_sdk_1.6_cc3220sf.zipProject to perform coremark test on cc3220sf. I ported to cc3220sf launchpad, using CCSv7 on Win7 / 64-bit.Instructions:1. Unzip this archive into your CCSv7 workspace2. Download coremark source archive from:www.eembc.org/.../download.php You will be asked to register as a user. 3. Open the coremark archive, probably with 7zip. Select all the source files in the archive, ignoring the folders, and drag into the coremark_v1.0_sdk_1.6 directory. (You may also want to drag the doc folder over, but the other folders are ports to specific platforms.) 4. In CCSv7, import the project into the workspace, telling CCS to search the workspace for projects.5. Build and Debug. Makefiles are ignored by CCS. Output will show up in the CIO window of CCSv7. I get the following output:[Cortex_M4_0] microsecs per tick = 10002K performance run parameters for coremark.CoreMark Size : 666Total ticks : 56818Total time (secs): 56Iterations/Sec : 107Iterations : 6000Compiler version : TI v16.9.6.LTSCompiler flags : -mv7M4 --code_state=16 --float_support=vfplib -me -O4 --opt_for_speed=5 -g --define=NORTOS_SUPPORTMemory location : code in FLASH, data in SRAMseedcrc : 0xe9f5crclist : 0xe714crcmatrix : 0x1fd7crcstate : 0x8e3acrcfinal : 0xa14cCorrect operation validated. See readme.txt for run and reporting rules.6. You can change between code in SRAM or code in FLASH by alternating between the two linker command files in the project (CC3220SF_LAUNCHXL_NoRTOS.cmd, CC3200SF_LAUNCHXL_NoRTOS_sram.cmd). Note that the text printed on the console regarding "Compiler flags", "Compiler version", and "Memory location" are NOT automatically generated, but are defined as macros in cc3220SF/core_portme.h.
Cameron, could you run the benchmark on a TM4C1294 with flash prefetch buffers disabled, as described on p. 608 of the datasheet ( )?
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