Hi Team,
The customer uses UART1 to receive data and uses FREERTOS.
UART1 is configured to enable the FIFO, and the 1/4 FIFO triggers the interrupt, which is 4 bytes into the receive interrupt.
During debugging, he found that interrupts often cannot be triggered, especially when the CPU load is high. He sends 4 bytes at a time, about five or six times, there will be one interruption.
He printed the register status and found that the FIFO was always empty when he sent the data. Data can't enter FIFO.
Customer would like to reslove this issue.
The code snippet is as follows. Figure 2 shows the register status printed when the data has not been interrupted.
