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CC3220MODA: CC3220MODA questions

david s
Genius 3005 points

Part Number: CC3220MODA
Other Parts Discussed in Thread: CC3220S, CC3220MOD,

Hi,

I have several questions below regarding CC3220MODA spec:

1) nRESET and VBAT_RESET connection

I copied an excerpt from the page 15 of the spec below and put my questions inline:

There is an internal, 100 kΩ, pull-up resistor option from the nRESET pin to VBAT_RESET. Note: VBAT_RESET is not connected to VBAT1 or VBAT2 within the module. The following connection schemes are recommended:

• Connect nRESET to a switch, external controller, or host, only if nRESET will be in a defined state under all operating conditions. Leave VBAT_RESET unconnected to save power.

Q: If VBAT_RESET is unconnected, where does VIN_DCDC_ANA (pin 37 of the main CC3220 device that is connected to VBAT_RESET pin inside the module) get power from? 

• If nRESET cannot be in a defined state under all operating conditions, connect VBAT_RESET to the main module power supply (VBAT1 and VBAT2). Due to the internal pullup resistor a leakage current of 3.3 V / 100 kΩ is expected.

Q: If VBAT_RESET is connected to main supply then nRESET would be connected through 100 kOhm resistor to the main supply. As implied by section 7-2-2 there should also be a capacitor inside the module to make sure there is ~5ms power-on reset happening. Is that correct? Does the statement about 3.3V/100 kOhm leakage imply that the leakage current will always be there, or the leakage will happen only if nRESET is driven 0 externally?

 

2) SOP values for factory restore 

For factory restore, page 66 says: 

The restore process is performed by calling software APIs, or by pulling or forcing SOP[2:0] = 110 pins and toggling the nRESET pin from low to high.


However, table 6-5 on page 67 specifies SOP[2:0]=011 for factory reset. 

Q: Which SOP setting is correct for factory reset?

 

3) Typical application schematic

On page 74, 5 GPIO pins are highlighted to be pulled out to aid in debug: GPIO_03, GPIO_04, GPIO_05, GPIO_06, GPIO_07.

Q: What is the meaning of these GPIOs?

Q: For flash programming, I am thinking to use GPIO_01/GPIO_02 for UART and use the same set of signals as recommended for CC3220S device typical application schematic: GPIO_01, GPIO_02, nRESET, SOP[2:0]. Is it okay to do so?

 

4) RF guidelines

Q: In Figure 7-2, if I don't need the U.FL connector, can I remove it (while leaving the rest of the RF routing the same) and still be able to reuse the certification?

Q: In Figure 7-6, how much is the recommended copper-to-board top edge clearance (if using MODA module)?

 

5) Input 5V to 3.6V conversion

Q: I need to put an LDO on board to convert the board input 5V to 3.6V to supply the module. If the exact layout style of the LDO in CC3220S launchpad is followed, will there be any issues during certification? Does LDO on the board anyhow impact the eligibility of TI certification re-use?

 

Thanks,

David

  • 0
    TI__Guru 63006 points
    Hi David,

    See answers below.

    Br,
    Kobi

    Q: If VBAT_RESET is unconnected, where does VIN_DCDC_ANA (pin 37 of the main CC3220 device that is connected to VBAT_RESET pin inside the module) get power from?
    A: Pin 37 (VIN-DCDC_ANA) is connected via VBAT1, not the VBAT_RESET pin. The VBAT_RESET pin is a dedicated connection to pull up the internal 100K ohm resistor.

    Q: If VBAT_RESET is connected to main supply then nRESET would be connected through 100 kOhm resistor to the main supply. As implied by section 7-2-2 there should also be a capacitor inside the module to make sure there is ~5ms power-on reset happening. Is that correct? Does the statement about 3.3V/100 kOhm leakage imply that the leakage current will always be there, or the leakage will happen only if nRESET is driven 0 externally?
    A: You are correct, there is a internal capacitor to ensure the timing is met. There is a 10nF capacitor from the nRESET pin to GND. In addition, there will be n leakage in the 100Kohm resistor if you do not connect VBAT-RESET to the main supply as it will be left floating, thus not connected.

    Q: Which SOP setting is correct for factory reset?
    A: SOP2 = 0, SOP1 = 1, SOP0 = 1 (then perform power on reset - POR).

    Q: What is the meaning of these GPIOs?
    A: 03 - WL_RS232_TX
    04 - WL_RS232_RX
    05 - WL_UART_TX
    06 - GPIO
    07 - NWP_UART_TX
    Those should be kept for TI proprietary debug. They may be used by us in case of a future issue that will require specific technical investigation.

    Q: For flash programming, I am thinking to use GPIO_01/GPIO_02 for UART and use the same set of signals as recommended for CC3220S device typical application schematic: GPIO_01, GPIO_02, nRESET, SOP[2:0]. Is it okay to do so?
    A: It is ok as long as you keep GPIO_01 & GPIO_02 for the UART (avoiding contention with another signals).

    Q: In Figure 7-2, if I don't need the U.FL connector, can I remove it (while leaving the rest of the RF routing the same) and still be able to reuse the certification?
    A: Note that we offer 2 parts. One is the CC3220MOD that requires and external antenna (that is it is not part of the module itself) and the CC3220MODA which has an integral antenna (you cannot change the antenna). For the CC3220MOD you can remove the antenna, but note that for regulatory testing you may want to have an option for doing this testing if needed, you can always depopulate on your final design. But in short there should be no issue in removing the connector, but its always best to check with your regulator house to ensure you still meet the modular requirements.

    Q: In Figure 7-6, how much is the recommended copper-to-board top edge clearance (if using MODA module)?
    A: I am not sure I understand your question. The module should overhang the edge of the board by 1mm and there should be no copper under the module (6 mm from the edge of the board. Also to the left and right there should be 6 mm of clearance. Outside of this there is no requirement for how close the copper can go to the edge of the board. That would be based on your design rules.

    Q: I need to put an LDO on board to convert the board input 5V to 3.6V to supply the module. If the exact layout style of the LDO in CC3220S launchpad is followed, will there be any issues during certification? Does LDO on the board anyhow impact the eligibility of TI certification re-use?
    A: With any certification, even a modular one, the end integrator (customer) is still responsible to ensure that all the regulatory requirements are met. That means that at the product level radiated spurious still needs to be met and may need to be tested. Using a different LDO or even changing the layout will not affect the re-use of the modular certification, as the main area of re-use is the RF performance. So in short, using the same layout and LDO is good as you will have confidence that the requirement is a pass, but changing the layout does not affect the core of the RF as at the product level you still need to meet all requirements.
  • 0 in reply to Kobi Leibovitch
    Genius 3005 points

    Hi Kobi,

    Thanks a lot for detailed replies. Please find my follow up questions below.

    Q: If VBAT_RESET is unconnected, where does VIN_DCDC_ANA (pin 37 of the main CC3220 device that is connected to VBAT_RESET pin inside the module) get power from? 
    A: Pin 37 (VIN-DCDC_ANA) is connected via VBAT1, not the VBAT_RESET pin. The VBAT_RESET pin is a dedicated connection to pull up the internal 100K ohm resistor.

    [David] The document contradicts with that statement, on page 15 it states that VBAT_RESET is connected to pin 37 of CC3220 device (column 4 in the table). This causes confusion. Thanks for clarifying.

    Q: If VBAT_RESET is connected to main supply then nRESET would be connected through 100 kOhm resistor to the main supply. As implied by section 7-2-2 there should also be a capacitor inside the module to make sure there is ~5ms power-on reset happening. Is that correct? Does the statement about 3.3V/100 kOhm leakage imply that the leakage current will always be there, or the leakage will happen only if nRESET is driven 0 externally?
    A: You are correct, there is a internal capacitor to ensure the timing is met. There is a 10nF capacitor from the nRESET pin to GND. In addition, there will be n leakage in the 100Kohm resistor if you do not connect VBAT-RESET to the main supply as it will be left floating, thus not connected.

    [David] I need to make sure I correctly understand VBAT_RESET and nRESET connection. Is the below scheme correct (R=100kOhm, C=10nF)? 

    VBAT_RESET ---/|/|/|/|/-------nRESET --------||----------GND

    Are there any other elements or drivers on VBAT_RESET and nRESET pins internally? I am not sure why there should be 3.3V/100kOhm leakage when VBAT_RESET is connected to VBAT1 and nRESET is not driven to 0.

    I plan to connect VBAT_RESET to VBAT1 and also I plan to connect a tactile switch on nRESET to be able to reset manually. Let me know if you see any issues.

    Q: Which SOP setting is correct for factory reset?
    A: SOP2 = 0, SOP1 = 1, SOP0 = 1 (then perform power on reset - POR). 

    [David] The SOP value is inaccurate on page 66 of the document. Thanks for confirming the correct setting.

    Q: What is the meaning of these GPIOs?
    A: 03 - WL_RS232_TX
    04 - WL_RS232_RX
    05 - WL_UART_TX
    06 - GPIO
    07 - NWP_UART_TX
    Those should be kept for TI proprietary debug. They may be used by us in case of a future issue that will require specific technical investigation. 

    [David] Ok, but I need to use ADC inputs on pins 3,4 and 5. Can I pull these pins out but at the same time use those as ADC inputs? There will be an opamp driving these pins on the board.

    Thanks for your answers.

    David

    Q: In Figure 7-2, if I don't need the U.FL connector, can I remove it (while leaving the rest of the RF routing the same) and still be able to reuse the certification?
    A: Note that we offer 2 parts. One is the CC3220MOD that requires and external antenna (that is it is not part of the module itself) and the CC3220MODA which has an integral antenna (you cannot change the antenna). For the CC3220MOD you can remove the antenna, but note that for regulatory testing you may want to have an option for doing this testing if needed, you can always depopulate on your final design. But in short there should be no issue in removing the connector, but its always best to check with your regulator house to ensure you still meet the modular requirements.

  • 0 in reply to david s
    TI__Guru 63006 points
    Q: Ok, but I need to use ADC inputs on pins 3,4 and 5. Can I pull these pins out but at the same time use those as ADC inputs? There will be an opamp driving these pins on the board.
    A: As those are not typically used (07-NWP_UART_TX is more often needed), you can avoid the recommendation and use the 3 lines as your ADC input (note that it will not allow us to fully debug your program if it uses the lines for the ADC, but again this type of debug is very rare).
  • 0 in reply to Kobi Leibovitch
    Genius 3005 points

    Alright, thanks a lot for quick response. Please address the following as well so that we can close this:

    Q: If VBAT_RESET is connected to main supply then nRESET would be connected through 100 kOhm resistor to the main supply. As implied by section 7-2-2 there should also be a capacitor inside the module to make sure there is ~5ms power-on reset happening. Is that correct? Does the statement about 3.3V/100 kOhm leakage imply that the leakage current will always be there, or the leakage will happen only if nRESET is driven 0 externally?

    A: You are correct, there is a internal capacitor to ensure the timing is met. There is a 10nF capacitor from the nRESET pin to GND. In addition, there will be n leakage in the 100Kohm resistor if you do not connect VBAT-RESET to the main supply as it will be left floating, thus not connected.

    [David] I need to make sure I correctly understand VBAT_RESET and nRESET connection. Is the below scheme correct (R=100kOhm, C=10nF)?

    VBAT_RESET ---/|/|/|/|/-------nRESET --------||----------GND

    Are there any other elements or drivers on VBAT_RESET and nRESET pins internally? I am not sure why there should be 3.3V/100kOhm leakage when VBAT_RESET is connected to VBAT1 and nRESET is not driven to 0.

    I plan to connect VBAT_RESET to VBAT1 and also I plan to connect a tactile switch on nRESET to be able to reset manually. Let me know if you see any issues.

    Thanks,

    David

  • 0 in reply to david s
    TI__Guru 63006 points
    Q: I need to make sure I correctly understand VBAT_RESET and nRESET connection. Is the below scheme correct (R=100kOhm, C=10nF)?
    VBAT_RESET ---/|/|/|/|/-------nRESET --------||----------GND
    A: yes, this is the correct configuration.

    Q: Are there any other elements or drivers on VBAT_RESET and nRESET pins internally? I am not sure why there should be 3.3V/100kOhm leakage when VBAT_RESET is connected to VBAT1 and nRESET is not driven to 0.
    A: The point we are making here is that if you tie VBAT_RESET to VBAT, then when you reset the module, you will have the leakage. On the other hand, if you are driving the signal from the host (say a GPIO), then there is no pull up and thus the external leakage is not there.

    Q: I plan to connect VBAT_RESET to VBAT1 and also I plan to connect a tactile switch on nRESET to be able to reset manually. Let me know if you see any issues.
    A: I see no issue with this.

    Br,
    Kobi
  • 0 in reply to Kobi Leibovitch
    Genius 3005 points
    Thanks!

    David