Part Number: CC2592
Other Parts Discussed in Thread: CC2530
R+jX of the antenna port not listed in the datasheet of the CC2592. What is the impedance?
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Can you provide the algorithms to calculate the passives for the matching circuits off your "optimized reference designs" when the stack-up / dielectric are changed? Since you do not provide the R+jX I cannot simply calculate that my self.
This is the stack I must use. Doing any kind of antenna turning is going to be a nightmare with no reference R+jX.
|
Thickness |
Thickness (mm) |
Layer |
Tolerance |
Tolerance (mm) |
|
1 mil |
.025 |
Solder Mask |
±0.25mil |
±0.01 |
|
1.5 mil |
.04 |
1 oz copper |
+0.5mil |
±0.02 |
|
13 mil |
.33 |
FR4 Prepreg |
|
|
|
0.7 mil |
.02 |
0.5 oz copper |
|
|
|
28 mil |
.7 |
FR4 Core |
|
|
|
0.7 mil |
.02 |
0.5 oz copper |
|
|
|
13 mil |
.33 |
FR4 Prepreg |
|
|
|
1.5 mil |
.04 |
1 oz copper |
+0.5mil |
±0.02 |
|
1 mil |
.025 |
Solder Mask |
±0.25mil |
±0.01 |
PCB Substrate dielectric constant of 3.95 @ 1GHz
Got our boards back from the manufacture and there is a weird problem. The boards work perfectly with Smart RF Studio, using the SmartRF05EB. I can fully control my board through that software. The interesting problem is when it comes to programming. I can erase & program but it fails on trying to verify. Do you have any guess on what could be the issue?
We are using cc2530 and just trying to load up the bootloader. 2 out of our 6 boards can flash and verify perfectly. However, every single one of those boards works flawlessly with Smart RF studio. I am really puzzled what can be causing this.
On the ones that work, its pulled low. But on the ones that don't work it's pulled high. I have logic analyzed one of the ones that pull high as it is being plugged to the debugger. It is interesting that it looks like it does not start pulled high but pulls high after. I will attach a few screenshots of the capture.
This is a view of the last "block" of data zoomed in a bit.
Here is the Matlab file (I can do CVS if you have something to read it)
Just did a capture of one working and there is only one difference between the two. I attached screenshots of the two captures. The first one is from a board that cannot be programmed (line never gets pulled back to low) and the seconds one is from one that can (line gets pulled to low)
[Not Working Startup]
[Working Startup]
The reset signals look the same, I did notice the reset lines looking like they coupled with the DD line for some reason. However, I busted out an EVM board to compare against and the coupling was there too.
No pull-ups or the debug lines and I am able to read the page on the failing units. The same problem persists in slow mode as well.
Hi, can you send a logic data with DC, DD and RESET signals in the same plot?
Thanks
Sure thing. The top one is the startup of a working board connected to a cc debugger and the bottom one is from a non-working board. I also attached Matlab data for each capture.
Working Board Startup
Non-Working Board Startup
Matlab files
I found the issue out and would like to report if you run VCC to the DCOUPL pin like a derp like I did then you will have these erratic behaviors. I am actually surprised some of them kinda worked 3.6v to a 1.8v pin I figured it would just be fried. Good job making it pretty high tolerances TI.