CC2530 ZNP Pin configuration

Pavel Kosenko

Other Parts Discussed in Thread: CC2530

In CC2530ZNP Interface specification we can see three configuration of pin. It is Main pin configuration, Alternate pin configuration and ZNP Kit pin configuration.

How i understand the first I can get CC2530ZNP_MK compile option, the last CC2530_MK..But how can get Alternate pin configuration for CC2530??

over 8 years ago

0 YiKai Chen over 8 years ago

Guru 735685 points

It's described in chapter 2 CC2530-ZNP physical Interface:
If the CFG1 pin is high, the CC2530-ZNP will use the SPI transport mode in the main pin configuration listed below. Otherwise, it will use the UART transport mode in the alternate pin configuration listed below. The ZNP Kit pin configuration is used by the ZNP kit target board. The pin-out diagram of the CC2530 can be found in [R2].

0 Pavel Kosenko over 8 years ago in reply to YiKai Chen

Genius 4540 points

You right about documetntation. But when I see source code for ZNP I see initialisation only for Main Configuration and for ZNP Kit pin configuration.

#if defined CC2530_MK
void npSpiInit(void)  // TODO - hard-coded for USART0 alt1 SPI for now.
{
  if (ZNP_CFG1_UART == znpCfg1)
  {
    return;
  }

  /* Set bit order to MSB */
  U0GCR |= BV(5);

  /* Set UART0 I/O to alternate 1 location on P1 pins. */
  //PERCFG |= 0x02;  /* U1CFG */

  /* Mode select UART1 SPI Mode as slave. */
  U0CSR = NP_CSR_MODE;

  /* Select peripheral function on I/O pins. */
  P0SEL |= 0x3C;  /* SELP0_[5:2] */

  /* Give UART1 priority over Timer3. */
  //P2SEL &= ~0x20;  /* PRI2P1 */

  /* Set RDY to inactive high. */
  NP_RDYOut = 1;

  /* Select general purpose on I/O pins. */
  P1SEL &= ~(NP_RDYOut_BIT);  /* P1.0 SRDY - GPIO */
  P2SEL &= ~(NP_RDYIn_BIT);   /* P2.0 MRDY - GPIO */

  /* Select GPIO direction */
  P1DIR |= NP_RDYOut_BIT;  /* P1.0 SRDY - OUT */
  P2DIR &= ~NP_RDYIn_BIT;  /* P2.0 MRDY - IN */

  /* Falling edge on P2 pins triggers interrupt. */
  PICTL |= BV(3);  /* P2ICON */

  /* Trigger an interrupt on MRDY input. */
  P2IFG &= ~NP_RDYIn_BIT;
  P2IEN |=  NP_RDYIn_BIT;
  IEN2 |= 0x02;

  dmaInit();

  U0CSR |= CSR_RE;
}
#else
void npSpiInit(void)
{
  if (ZNP_CFG1_UART == znpCfg1)
  {
    return;
  }

  /* Set bit order to MSB */
  U1GCR |= BV(5);

  /* Set UART1 I/O to alternate 2 location on P1 pins. */
  PERCFG |= 0x02;  /* U1CFG */

  /* Mode select UART1 SPI Mode as slave. */
  U1CSR = NP_CSR_MODE;

  /* Select peripheral function on I/O pins. */
  P1SEL |= 0xF0;  /* SELP1_[7:4] */

  /* Give UART1 priority over Timer3. */
  P2SEL &= ~0x20;  /* PRI2P1 */

  /* Set RDY to inactive high. */
  NP_RDYOut = 1;

  /* Select general purpose on I/O pins. */
  P0SEL &= ~(NP_RDYIn_BIT);   /* P0.3 MRDY - GPIO */
  P0SEL &= ~(NP_RDYOut_BIT);  /* P0.4 SRDY - GPIO */

  /* Select GPIO direction */
  P0DIR &= ~NP_RDYIn_BIT;  /* P0.3 MRDY - IN */
  P0DIR |= NP_RDYOut_BIT;  /* P0.4 SRDY - OUT */

  P0INP &= ~NP_RDYIn_BIT;  /* Pullup/down enable of MRDY input. */
  P2INP &= ~BV(5);         /* Pullup all P0 inputs. */

  /* Falling edge on P0 pins triggers interrupt. */
  PICTL |= BV(0);  /* P0ICON */

  /* Trigger an interrupt on MRDY input. */
  P0IFG &= ~NP_RDYIn_BIT;
  P0IEN |=  NP_RDYIn_BIT;
  P0IE = 1;

  dmaInit();

  U1CSR |= CSR_RE;
}
#endif

But in Alternate pin cofiguration MRDY and SRDY is P1_6 and P1_7

0 YiKai Chen over 8 years ago in reply to Pavel Kosenko

Guru 735685 points

If you read section 2.3.3.3 Signal Description, it says:

Two additional signals are required for SPI transaction handling and power management:
 MRDY: Master ready, an active low signal. This signal is set by the application processor when it has data ready to send to the CC2530. This signal can either be controlled independently or it can be hardwired to the slave select signal. The RPC sequence diagrams in this document assume MRDY is hardwired to SS.
 SRDY: Slave ready, a bi-modal signal. This signal is set by the CC2530 when it is ready to receive or send data. When set low, it indicates the CC2530 is ready to receive data. When set high during an SPI POLL or SREQ transaction it indicates the CC2530 is ready to send data. When set high during an SPI AREQ transaction it indicates the CC2530 is done receiving data.

MRDY and SRDY are only needed by SPI interface.

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CC2530 ZNP Pin configuration