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CC2538EMK: Decreasing the receiving range/sensitivity using CCA threshold

Part Number: CC2538EMK
Other Parts Discussed in Thread: CC2538, , Z-STACK

I am trying to decrease the receiver sensitivity of a node.  suggested here that I focus on the CCA threshold to be able to do it. But the problem is that even when I set the threshold, say -20, using RFCORE_XREG_CCACTRL0 = 0x35 knowing that  CC2538_RSSI_OFFSET is -73, the device still gets packets with RSSI lower than -20 (e.g. -76). i.e. no change happens. I also tried that with the 4 CCA modes (0,1,2,3) but still the same.

I am using different firmware (RIOT-OS installed in Openmote-CC2538, CC2538EMK devices) and I am sure there is more than setting CCA value to make it work such as setting the RFCORE_XREG_RFC_OBS_CTRL0/1 with the right values. I also tried to map settings in your Zigbee firmware but I could not succeed to enable CCA.

I would really appreciate your input on the matter.

Here are some of the codes/definitions for the CC2538 module in RIOT-OS for your reference:


 * @brief Values for use with CCTEST_OBSSELx registers.
enum {
    rfc_obs_sig0 = 0,
    rfc_obs_sig1 = 1,
    rfc_obs_sig2 = 2,

 * @brief Values for RFCORE_XREG_RFC_OBS_CTRLx registers.
enum {
    constant_value_0 = 0x00, /**< Constant value 0 */
    constant_value_1 = 0x01, /**< Constant value 1*/
    rfc_sniff_data   = 0x08, /**< Data from packet sniffer. Sample data
                                  on rising edges of sniff_clk.*/
    rfc_sniff_clk    = 0x09, /**< 250kHz clock for packet sniffer data.*/
    rssi_valid       = 0x0c, /**< Pin is high when the RSSI value has
                                  been updated at least once since RX was
                                  started. Cleared when leaving RX.*/
    demod_cca        = 0x0d, /**< Clear channel assessment. See FSMSTAT1
                                  register for details on how to configure
                                  the behavior of this signal. */
    sampled_cca      = 0x0e, /**< A sampled version of the CCA bit from
                                  demodulator. The value is updated whenever
                                  a SSAMPLECCA or STXONCCA strobe is issued.*/
    sfd_sync         = 0x0f, /**< Pin is high when a SFD has been received
                                  or transmitted. Cleared when leaving
                                  RX/TX respectively. Not to be confused
                                  with the SFD exception.*/
    tx_active        = 0x10, /**< Indicates that FFCTRL is in one of the TX
                                  states. Active-high.*/
    rx_active        = 0x11, /**< Indicates that FFCTRL is in one of the
                                  RX states. Active-high. */
    ffctrl_fifo      = 0x12, /**< Pin is high when one or more bytes are
                                  in the RXFIFO. Low during RXFIFO overflow. */
    ffctrl_fifop     = 0x13, /**< Pin is high when the number of bytes
                                  in the RXFIFO exceeds the programmable
                                  threshold or at least  one complete
                                  frame is in the RXFIFO. Also highduring
                                  RXFIFO overflow. Not to be confused with
                                  the FIFOP exception.*/
    packet_done      = 0x14, /**< A complete frame has been received.
                                  I.e., the number of bytes set by the
                                  frame-length field has been received.*/
    rfc_xor_rand_i_q = 0x16, /**< XOR between I and Q random outputs.
                                  Updated at 8 MHz.*/
    rfc_rand_q       = 0x17, /**< Random data output from the Q channel
                                  of the receiver. Updated at 8 MHz.*/
    rfc_rand_i       = 0x18, /**< Random data output from the I channel
                                  of the receiver. Updated at 8 MHz */
    lock_status      = 0x19, /**< 1 when PLL is in lock, otherwise 0 */
    pa_pd            = 0x20, /**< Power amplifier power-down signal */
    lna_pd           = 0x2a, /**< LNA power-down signal*/
    disabled         = 0xff, /**< disabled */

 * @name    RF CORE observable signals settings
#ifndef CONFIG_CC2538_RF_OBS_0
#define CONFIG_CC2538_RF_OBS_0      tx_active
#ifndef CONFIG_CC2538_RF_OBS_1
#define CONFIG_CC2538_RF_OBS_1      rx_active
#ifndef CONFIG_CC2538_RF_OBS_2
#define CONFIG_CC2538_RF_OBS_2      rssi_valid

/* Default configuration for cc2538dk or similar */
#ifndef CONFIG_CC2538_RF_OBS_SIG_0_PCX
#define CONFIG_CC2538_RF_OBS_SIG_0_PCX  0   /* PC0 = LED_1 (red) */
#ifndef CONFIG_CC2538_RF_OBS_SIG_1_PCX
#define CONFIG_CC2538_RF_OBS_SIG_1_PCX  1   /* PC0 = LED_2 (red) */
#ifndef CONFIG_CC2538_RF_OBS_SIG_2_PCX
#define CONFIG_CC2538_RF_OBS_SIG_2_PCX  2   /* PC0 = LED_3 (red) */
#if ((CONFIG_CC2538_RF_OBS_SIG_2_PCX > 7) || \
     (CONFIG_CC2538_RF_OBS_SIG_1_PCX > 7) || \
     (CONFIG_CC2538_RF_OBS_SIG_0_PCX > 7))
#error "CONFIG_CC2538_RF_OBS_SIG_X_PCX must be between 0-7 (PC0-PC7)"


 * @name    RF CORE observable signals settings
 * @{
#define CONFIG_CC2538_RF_OBS_SIG_0_PCX  5   /* PC5 */
#define CONFIG_CC2538_RF_OBS_SIG_1_PCX  6   /* PC6 */
#define CONFIG_CC2538_RF_OBS_SIG_2_PCX  7   /* PC7 */
/** @} */

static void _cc2538_observable_signals(void)
    /* Select on which pin PC0:7 should the selected observable signals
       be wired through, the signal is selected in CONFIG_CC2538_RF_OBS_%
       and the pin in CONFIG_CC2538_RF_OBS_SIG_%_PCX */
    if (IS_USED(MODULE_CC2538_RF_OBS_SIG)) {
        if (CONFIG_CC2538_RF_OBS_0 != disabled) {
            *(&CCTEST_OBSSEL0 + CONFIG_CC2538_RF_OBS_SIG_0_PCX) = \
                CCTEST_OBSSELX_EN | rfc_obs_sig0;
        if (CONFIG_CC2538_RF_OBS_1 != disabled) {
            *(&CCTEST_OBSSEL0 + CONFIG_CC2538_RF_OBS_SIG_1_PCX) = \
                CCTEST_OBSSELX_EN | rfc_obs_sig1;
        if (CONFIG_CC2538_RF_OBS_2 != disabled) {
            *(&CCTEST_OBSSEL0 + CONFIG_CC2538_RF_OBS_SIG_2_PCX) = \
                CCTEST_OBSSELX_EN | rfc_obs_sig2;

void cc2538_init(void)
    /* Enable RF CORE clock in active mode */
    /* Enable  RF CORE  clock in sleep mode */
    /* Enable  RF CORE  clock in PM0 (system clock always powered down
        in PM1-3) */
    /* Wait for the clock enabling to take effect */
    while (!(SYS_CTRL_RCGCRFC & 1UL) || \
           !(SYS_CTRL_SCGCRFC & 1UL) || \
           !(SYS_CTRL_DCGCRFC & 1UL)
           ) {}

    /* Register Setting updates for optimal performance, RM section 23.15 */
    RFCORE_XREG_AGCCTRL1    = 0x15;
    RFCORE_XREG_FSCAL1      = 0x01;
    ANA_REGS_IVCTRL         = 0x0B;

    /* Enable AUTOCRC and AUTOACK by default*/

    /* Disable RX after TX, let upper layer change the state */

    /* Disable source address matching and pending bits */

    /* Set FIFOP_THR to its max value*/

    /* Set default IRQ */

    /* Enable all RF CORE error interrupts */
                         RXUNDERF | RXOVERF | NLOCK;


    #ifdef CC2592_EMBEDDED
        #if (CC2592_EMBEDDED == 1)
            RFCORE_XREG_RFC_OBS_CTRL0 = 0x6A; //0x20; //0x6A;
            RFCORE_XREG_RFC_OBS_CTRL1 = 0x68; //0x2a; //0x68;
            RFCORE_XREG_RFC_OBS_CTRL0 = 0x20; //0x20; //0x6A;
            RFCORE_XREG_RFC_OBS_CTRL1 = 0x2a; //0x2a; //0x68;
        CCTEST_OBSSEL2 = 0x80;
        CCTEST_OBSSEL3 = 0x81;    

    /* Remaingin Code... */

With openmote-cc2538 normally the following registers have the following values


I tried to change them to the following to enable cca:

RFCORE_XREG_RFC_OBS_CTRL1 = 0x0d;  // also 0x0e

Please help,


  • Hello Ahed,

    You can review the TRM for more information concerning these registers.  In Z-Stack and RF examples, I've only ever seen RFC_OBS_CTRL0/1 modified to control signals to RF frontend chips.  You can perhaps also reference the CC2538-SW including PER test for a better understanding of setting CCA_THR through CCACTRLX registers. It may be better to have your third-party software questions addressed by the Contiki community.