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cc2540/cc2541 Data Sheet Error for UART Pin Config

SATTAR MALOKANI
Intellectual 555 points
Other Parts Discussed in Thread: CC2540

Hi TI Guys,

Please fix this bug in data sheet. In user manual data sheet for cc2540/41 (Revised April 2014) on page 81 it state that UART1 is on alternate location 1 which is P0 and pin 4 tx and pin 5 Rx,  according to datasheet physical pin locations are ok but software configurations are not ok.

If I want to use UART1 at alternate location 1, according to datasheet register configuration for UART1 at Alternate location 1 should be:

PERCFG &= ~0x02;    /* Configure UART1 for alternative 1 */

P0SEL |= 0x30;      /* Configure Port P0 pins for UART Peripheral function */

but this configuration is only working for Tx, and Rx no working. And I spent couple of days to figure out why Rx no responsive. i also posted here but did not find good response fro TI. 

The interesting thing is when I changed above config to below configuration:

PERCFG |= 0x01; 

P0SEL |= 0x30;

but according datasheet this configuration is for Alternative2 (P1) and UART1. but this configuration is working on Alternative1 (P0) UART1. So there is error in datasheet for configurations of UART1. 

I hope this information will also help others.

Please ugrade the datasheet to avoid confusion to others also.

regards,

Sattar Malokani

  • 0
    TI__Genius 10955 points
    You need to read the whole Section 7.6. Then you will see that by default, USART0 has priority over USART1 for using the P0 pins. With your second setting, you are moving USART0 to alternative2 pin mapping, thus removing the conflict. Another way of resolving the conflict is to write to P2DIR.PRIP0 as described in Section 7.6.5. So your configuration should be:
    PERCFG &= ~0x02; /* Configure UART1 for alternative 1 */
    P2DIR = (P2DIR & 0x3F) | 0x40; /* Give USART1 priority on P0*/
    P0SEL |= 0x30; /* Configure Port P0 pins for UART Peripheral function */

    I can see that this part of the user guide can be a bit difficult to comprehend. But the information is correct.
  • 0 in reply to hec
    Intellectual 555 points

    Hi hec,

    Thanks for pointing me to correct direction, however I have still confusion in datasheet reading.

    to be very honest I already read these sections and with your recommendation again read but to be very frank I still did not get correct information. as in above comment you said that UASRT0 has priority over USART1 for using P0 pins. With flow control disable mean only P0_2 and P0_3 are available as preference. by default these pins will be active when selected as peripheral. By default USART0 should be active mean P0_2 and P0_3 pins as these have preference over USART1.

    In my code I did not give any priority, then why just Tx of USART1 become active with the following code.

    PERCFG &= ~0x02; /* Configure UART1 for alternative 1 */
    P0SEL |= 0x30; /

    by default Tx pin should also not be active because USART0 pins P0_2 and P0_3 have precedence to use. In section 7.6.5 uart0 has precedence to use P0.2 and P0.3 because I did not set P2DIR.PRIP0 to 01. From that what I understand that Tx of USART1 also should not be working. But this is not the case Tx is working fine for USART1 on default configuration.. This makes me really confuse.

    would you please explain following section I have copied from datasheet.

    7.6.4 USART 0

    P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to

    00, USART 0 has precedence. Note that if UART mode is selected and hardware flow control is disabled,

    USART 1 or Timer 1 has precedence to use ports P0.4 and P0.5.

    (In this above section if I do not use P2DIR.PRIP0 then this means USART1 has precedence to Use P0.4 and P0.5 as I did not use P2DIR.PRIP0 so precedence  should be P0.4 and P0.5 but this is not the case, as only tx is working there )

    7.6.5 USART 1

    P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to

    01, USART 1 has precedence. Note that if UART mode is selected and hardware flow control is disabled,

    USART 0 or Timer 1 has precedence to use ports P0.2 and P0.3.

    Thanks,

    regard

    sattar malokani

  • 0 in reply to SATTAR MALOKANI
    TI__Genius 10955 points

    I will try to explain as good as I can. What this means, is that if one of the USARTs is configured in UART mode with flow control disabled, the USART in question will not try to control its flow control pins. For instance, you may configure both USARTs as UART with flow control disabled, and configure both USARTs at alternative 1 location. In this case, USART0 will control P0.2 and P0.3, and USART1 will control P0.4 and P0.5. This will happen even if P2DIR.PRIP0 is 00 (meaning USART0 has priority over USART1), as USART0 doesn't have a peripheral function mapped to P0.4 and P0.5 in that configuration.

    In your case, you observed that the TX pin of USART1 was working, but not the RX pin. This case is actually not explained in Section 7.6.4 and 7.6.5 of the user guide, but if you look at the fourth paragraph of Section 7.6, you can read the following:

    Note that a peripheral normally is present at the selected location even if it is not used, and another peripheral that is to use the pins must be given higher priority. The exception is the RTS and CTS pins of a USART in UART mode with flow control disabled and the SSN pin of a USART configured in SPI master mode.

    So in this case, USART0 is presumably configured in SPI master mode (which is the default mode). In that case, the chip select (SSN) pin is not mapped to anything, meaning that USART1 is allowed to control P0.4. However, P0.5 is mapped to both the SPI clock signal of USART0 (which in master mode is an output) and the UART RX signal of USART1. With the default priority, this means that USART0 "wins".

    I hope this helps you getting a better understanding of the peripheral I/O mapping.

  • 0 in reply to hec
    Intellectual 555 points
    Hi Hec,

    thank you for clarifying my information. so this means information on datasheet is correct but not explained in clear way to be understood by me. from your information I understood but once more I need to read these section again to have complete understanding of all peripheral maping. thanks again.

    regards

    sattar malokani