Other Parts Discussed in Thread: CC2650
I've configured a :
* PWM timer that send events on rising edge
* UDMA is triggered on these events, each time, PWM match value is written to timer register. A ram buffer of size n contains these values. At end, an interrupt is raised when udma transfer is finished.
* generated signal is recorded using a logic analyser
Here is first setup :
UDMA buffer is :
static uint32_t _dataToTransfer[] = {20, 40, 20, 40, 20, 40};
Timer load value is 120, it means a 2.52µs period according to logic analyzer (I'm running a cc2650 @48MHz).
Here is resulting signal :
As you can see, we can find that buffer values have been written to PWM match counter on each PWM period. After the 6 transfers you can see some additional period, I thinkl it is because of delay introduced in UDMA transfer done interrupt (UDMA transfer is stopped but not timer, its match value is latest UDMA transferred last value 40)
Now I'm doing same test but with a smaller PWM period - 60 count ~ 1.28µs
As you can see, in some cases, I get a signal at high level during PWM period (1.28µs) + Next PWM High time (0.4µs) = 1.680µs
In some cases, PWM match value (from UDMA) is lost and signal stays high.
Does that mean that below a given PWM period, timer cannot load UDMA match value and do not take any match value (neither old one nor new one being loaded by UDMA)?
Lah
