Tool/software: TI-RTOS
Hello,
I am have read the Kernel User Guide - HeapBuff section. It reads"Be careful when specifying these runtime parameters. The blocksize needs to be a multiple of the worst-case structure alignment size. And bufSize should be equal to blockSize * numBlocks. The worst-case structure alignment is target dependent. On devices with a 32-bit architecture, the 8-byte alignment is used. The base address of the buffer should also be aligned to this same size."
I am running on a CC2650, and assume that it also uses the "8-byte alignment" [Please comment on the truth of this]. As I understand it, the MCU will user a character array as the heap, and in this case it will be 1280 bytes wide (see code below). I do not understand why a block size must be chosen, but I take it to mean that this particular code was written by a user who expects to write 10 objects of 128 bytes in size - I assume this since we are speaking of HeapBuf in which we must already know the size of data we will be writing (which should correspond to the block size?). If I am incorrect in this assumption, please explain me, as I do not understand why the number of blocks must be allocated to begin with.
Finally, to account for "worst-case structure alignment", should we create block sizes that are multiples of 8 for the CC2650 system? Thank you for your help!
HeapBuf_Params prms;
static char buf[1280];
HeapBuf_Handle heap;
Error_Block eb;
Error_init(&eb);
HeapBuf_Params_init(&prms);
prms.blockSize = 128;
prms.numBlocks = 10;
prms.buf = (Ptr)buf;
prms.bufSize = 1280;
heap = HeapBuf_create(&prms, &eb);
if (heap == NULL) {
System_abort("HeapBuf create failed");
}