Other Parts Discussed in Thread: CC2640,
My customer has the following questions. They amount to helping confirm their understanding from the data sheet, slide deck (CC2640 overview) to get a better understanding of the CC2640R2F inside topology and how best to interface with it given their space constraints.
Questions:
Figure 7-1 (CC2640R2F datasheet: SWRS204A –DECEMBER 2016–REVISED JANUARY 2017) depicts 3 application circuits. For our application, we are highly real estate limited, yet desire the highest path loss tolerance (highest output power & best receive sensitivity). I’d like to confirm a couple things:
Thanks!