1125: urgent issue because of signal output problems

Forum cut my above post, so here's the rest:
We know there's some jitter in transparent mode, but we expect the above behaviour is faulty and can be fixed by configuration.

Btw, we don't use the cal.from errata as we think it's not necessary for transparent mode; pls. tell me if this is wrong.

This is a real urgent serious issue, so thanks in advance for any help

Register settings:

  {CC112X_IOCFG3,            0x08},	
  {CC112X_IOCFG2,            0x09},	
  {CC112X_IOCFG1,            0xB0},	
  {CC112X_IOCFG0,            0x30},	
  {CC112X_SYNC_CFG1,         0x1f},	// gg--diff tx  // Rx = 1F tx 0b
  {CC112X_SYNC_CFG0,         0x17},		// not in Rx
  {CC112X_DEVIATION_M,       0x6F}, 
  {CC112X_MODCFG_DEV_E,      0x02}, 		// evtl. 03
  {CC112X_DCFILT_CFG,        0x1C},	
  {CC112X_PREAMBLE_CFG1,     0x00},	
  {CC112X_FREQ_IF_CFG,       0x33},	
  {CC112X_IQIC,              0xC6},	
  {CC112X_CHAN_BW,           0x0D},	  // Tx = 0x11
//---------------------------------------------
  {CC112X_MDMCFG1,           0x06}, 
  {CC112X_MDMCFG0,           0x4a},		// rx 4a tX 45
  {CC112X_DRATE2,            0x5A},	  // Tx 0x60
  {CC112X_DRATE1,            0x36},	  // Tx 0x62
  {CC112X_DRATE0,            0xE3},	  // Tx 0x4E
  {CC112X_AGC_REF,           0x20},	
  {CC112X_AGC_CS_THR,        0x19},	
  {CC112X_AGC_CFG1,          0x0a},	// gg--diff tx 	//Rx 0x0A  tx a9
  {CC112X_AGC_CFG0,          0xCF},	
  {CC112X_FIFO_CFG,          0x00},	
  {CC112X_SETTLING_CFG,      0x03},	
//---------------------------------------------
  {CC112X_FS_CFG,            0x14},	
  {CC112X_PKT_CFG2,          0x07},	
  {CC112X_PKT_CFG1,          0x00},	
  {CC112X_PKT_CFG0,          0x20},	
  {CC112X_PA_CFG2,           0x7F},	
  {CC112X_PA_CFG1,           0x56},	
  {CC112X_PA_CFG0,           0x7E},	
  {CC112X_IF_MIX_CFG,        0x00},	
  {CC112X_FREQOFF_CFG,       0x22},	
  {CC112X_ECG_CFG,           0x00},	
  {CC112X_SOFT_TX_DATA_CFG,  0x00},	
  {CC112X_FREQ2,             0x56},	
  {CC112X_FREQ1,             0xD0},	
  {CC112X_FREQ0,             0xA4},	
//---------------------------------------------
  {CC112X_IF_ADC0,           0x05},	
  {CC112X_FS_DIG1,           0x00},	
  {CC112X_FS_DIG0,           0x5F},	
  {CC112X_FS_CAL0,           0x0E},	
  {CC112X_FS_DIVTWO,         0x03},	
  {CC112X_FS_DSM0,           0x33},	
  {CC112X_FS_DVC0,           0x17},	
  {CC112X_FS_PFD,            0x50},	
  {CC112X_FS_PRE,            0x6E},	
  {CC112X_FS_REG_DIV_CML,    0x14},	
  {CC112X_FS_SPARE,          0xAC},	
  {CC112X_FS_VCO0,           0x81},	
//---------------------------------------------
  {CC112X_XOSC5,             0x0E},	
  {CC112X_XOSC3,             0xC7},	
  {CC112X_XOSC1,             0x07},	
  {CC112X_SERIAL_STATUS,     0x08}	

- You need to run the errata. This is to ensure correct VCO frequency and is equally relevant if you use the chip in transparent mode or in FIFO mode.

- I started to look at your register settings and the FREQ word does not correspond to 433MHz.

I will see if I can reproduce what you see.

I'll include the errata.

FREQ is 434.075 MHz (our default).

I sharpened some of the views, hopefully it leads you to the right track:
A. First of all flickering is less extreme if input frequency is exact at e.g. 1/2/4 kHz (below mentioning TX/RX means using 1125 in TX or RX with old analog module at the other side).
Watch the duty cycle of the output (input 50%), low phase is sometimes equal, sometimes much to short:
A1: 1125 on RX side

A2: 1125 on TX side

B. Now input is changed to 2.005kHz (every change to exact 1/2/4 kHz has almost same result). Flickering increases a lot:
B1: 1125 on RX side

B2: 1125 on TX side

C. 20% duty cycle and 1125 at both ends RX/TX; look at the output duty cycle:

forum screws the uploads ...; new try:

A1. 1125 on RX side

C. 20% duty cycle and 1125 at both ends RX/TX; look at the output duty cycle:

For RX we changed MDMCFG0 from 4A to 62h, which means TRANSPARENT_INTFACT to 4x and DATAFILTER_EN = Disabled; Viterbi doesn't have an effect.

-> Jitter became much more calm and even duty cycle is improved a bit. But I don't know how come and what's the price tag.. ?

Another positive effect is when I increase BW from 12.5. to e.g. 30kHz -> duty cycle improves by over 10%. But we design narrow band systems!

So obviously there is room for improvement, but we feel like commanding the Enterprise not knowing what button to press ...

TX: no findings so far.

Transparent mode has a finit resolution. Since the receive path has an ADC the data out will have a resolution given by the amout of decimation. Or to phrase it differently, the time resolution/ jitter will be 1/(RX BW * 8) given 1 in intermodulation. By adjusting the intermodulation the jitter is less.

When using transparent mode the data out should be oversampled since some glitches occur for low input signal strenghts.

TER,

not sure I can follow 'intermodulation': what do you mean, how to adjust in reality, which register can impact it.

Are our above findings/settings valid/allowed and make sense?

TX: why does TX also behave that way and how to calm it?

Sorry, typo, interpolation I intended to write.

Interpolation: MDMCFG0.transparent_intfact

The combination is allowed but it is recommended to use the datafilter, MDMCFG0.DATA_FILT_EN=1.

TER,
this makes sense.

Still open: what about TX, how to improve behaviour