frequency compensation mechanism of CC1120

The FREQOFF_EST value is updated when receiving a packet. For this to be the case the signal has to be within the bandwidth of the channel filter. Hence if you have a narrow channel and want to correct for temperature and voltage related frequency offset you actually have to receive a packet before getting an estimate for the offset. For a known offset you can take this into account by adjusting the FREQOFF register but for a variable offset you have to either use a TCXO to minimize the impact of voltage/ temperature/ aging or you may widen the RX bandwidth to ensure that you always can receive a signal given the frequency inaccuracy on the RX/TX side. It is also possible to use  the feedback to PLL feature, see presentation in my first post in this thread: http://e2e.ti.com/support/low_power_rf/f/156/t/201453.aspx

Required RX filter bandwidth can be approximated as :Signal BW  + 4*ppm xtal*Frequency of operation , where Signal BW of = Data rate + 2 x frequency deviation.

Example: 38.4 kbps data rate and +/-19.2 kHz deviation gives Signal BW of38.4 + 2 x 19.2 = 76.8 kHz

For modulation index m= 1, the frequency separation, which is  2 x frequency deviation, is equal to the data rate.  I.e m = 2 x frequency deviation / data rate

 Hello TER,

thank you for your response. I understand your information, but it does not answer my questions. So I have to ask again:

I always get values in FREQOFF_EST, even if I switch it off with FREQOFF_CFG.FOC_EN = 0. Why do I still get values?

Are there two different mechanism for frequency compensation within the cc1120?

How can I get detailed description of the internal frequency compensation mechanism?

My project is as follows:

The frequency of the transmitter is absolutely stable. It transmits Data in POCSAG format (2FSK, 1200 baud). So the transmitter doesn't matter for the frequency compensation.

The receivers based on cc1120 with an 32MHz crystal +-10ppm. But, depending of the board design one receiver board has an clock pulse with 32,000,314 Hz +-10ppm an other with 32,001,103 Hz +-10ppm and so on. The plan was to compensate the difference of the clock pulse with an individual "software" offset value in the FREQOFF[1-0] register. The value of the FREQ[2-0] should base on the 32MHz clock for each receiver the same.

How to handle with FREQOFF_EST?

RF-Frequency = FREQ[2-0] + FREQOFF[1-0](my calculated offset)

What is if the FREQOFF_EST tells me 0x000D?

a) RF-Frequency = FREQ[2-0] + FREQOFF[1-0](my calculated offset) + 0x000d

or b) RF-Frequency = FREQ[2-0] + new offset 0x000d (without old FREQOFF[1-0]

many thanks for response and best regards

Nico

A question on the side: Why do you want to compensate for offsets less than 1kHz?

Hello TER,

My RX frequency should be 439.875MHz. If I calculate with the theoretical 32,000,000Hz crystal clock I will get the FREQ[2-0] value 7206912.

Now I have one device with the 32,001,103Hz crystal clock. If I use here the same FREQ[2-0] value it will results in a 439.890MHz RX frequency. This is more than 1KHz deviation. It is more deviation (15KHz) than my bandwidth is.

The other device has a crystal clock of 32,000,314Hz, and so on. I do not want to calculate the FREQ[2-0] value for each device individually. I want to calculate with the theoretical 32MHz crystal clock and add or remove the individual deviation with an individual calculated FREQOFF[1-0] value. Because, if I want to switch to another RX frequency in that frequency band during operation I can use the theoretical calculation and the offset will always be the same.

I could do the compensation in my firmware, but it would be smarter and easier for me If I could do that with the cc1120 register. I only need some background information of the frequency compensation mechanism, see my posts above.

best regards

Nico

FREQEST is always calculated when receiving a sync word.

The chip calculates an estimate of the frequency offset in the register FREQOFF_EST. This estimate is calculated when receiving a SYNC word. Hence only small offsets is possible to compensate with this method since the signal has to fit the receiver bandwidth. In production it is possible to set the RX BW a few times wider than what will be used in the field then apply a signal with known frequency and read the FREQOFF_EST register. The FREQOFF register is then set to this value for this board and the RX BW is set back to what wil be used in the field. 

In the field the FREQOFF_EST register may be used to set a new value for FREQOFF over time when the aging and temperature change the crystal frequency. This method requires that the change in crystal frequency between each time FREQOFF is updated is small, ensuring that the signal is possible to receive at all time. I'm not sure if this method is reliable.

For a narrow band system we strongly recommend the use of TCXO to have a stable reference. It also depend on the standard if a TCXO is required due to phase noise requirements in a narrow channel.

Hi

I'm working with CC1101 to receive POCSAG messages (f=452.6MHz, Baud=1200, Ch=25KHz, Dev=4.5KHz).

CC1101 is configured with 2-FSK, FREQ=452.599792MHz, CHANSPC=25.39KHz, DRATE=1.19948kBaud, DEVIATN=4.364KHz, CHANBW=58KHz, FREQ_IF=457KHz.

RX FIFO and Important Status registers are polled at nearly 4-times the baud rate and sent to a serial port on a PC. During the whole packet reception, RX FIFO=0xFF, FREQEST=0x09, LQI=0x80, RSSI~0xE2.

What's the problem with the data? Which configuration is wrong?

Thank you in advance