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CC1125 ADC I and Q Data Samples and Clock on GPIO Pins (IOCFGx.GPIOx_CFG = 46)

Tilde the Hun
Prodigy 30 points
Other Parts Discussed in Thread: CC1175, CC1125

BACKGROUND

I note that the CC112X/CC1175 User's Guide (SWRU295E) describes a way to get I and Q ADC samples out on GPIO pins.  

This seems to be done by programming the IOCFGx registers (User's Guide page 71) in the register's fields named GPIOx_CFG, where "x" is 0 through 3.  The field values are given in table 10 on page 21 of the User's Guide, and decimal 46 is the value of interest in table 10. 

MY QUESTIONS

1. Only one bit is provided for each of I and Q.  I would guess the CC1125's ADCs are Sigma-Delta types and these are the serial outputs of the delta modulators.  Is this right?  If the ADC outputs are instead some other serial format, what is the format?  (I understand that a decimating filter is needed downstream of a Sigma-Delta.)

2. If the ADCs are indeed Sigma-Delta type, can you tell me the loop order (so that I may estimate the loop's noise shaping behavior)?

3. Is the ADC_CLOCK output to the GPIO pin a fixed frequency, e.g. a fixed divided version of XOSC?  If so, what is the fixed frequency or ratio?  Or does it change with certain register settings?  If it changes with settings, what settings does it change with?

4. I would guess that the ADC_CLOCK is intended to synchronize the ADC_I_DATA_SAMPLE and ADC_Q_DATA_SAMPLE at the destination device.  If so, should the rising or falling edge of ADC_CLOCK be used?

Thank You

  • 0
    TI__Guru**** 317180 points
    1) Yes, the delta sigma used has a single bit output. What you get on the pin is the direct output from the sigma delta

    3) The ADC is clocked on XOSC/2

    What are you going to use the I/Q data for? Note that clocking out a high speed signal on GPIOs will impact the performance of the chip. If you plan to use the I/Q data for demodulation, taking the data from a LVDS interface is an option. The data will then be clocked out with 2*XOSC speed.

    Program:

    IOCCFG3 0xB0

    IOCCFG2 0xB0

    Comment: Register setting for setting the output Pad’s in analogue transfer mode and digital drivers are set to high impedance.

    ADC_TEST 0x20

    ATEST 0x00

    ATEST_LVDS 0x02

    Comment: Registers setting for selecting IF-ADC data on LVDS interface.

    The LVDS data format is [I 1 Q 0].

    Also it's possible to take the I and Q data after the channel filter with a rate of 4*RXFilterBandwidth
  • 0 in reply to TER
    Prodigy 30 points

    Thank you TER.

    The I/Q data is needed for a custom legacy application (proprietary) not supported by the device's built-in demodulators.

    The LVDS option sounds attractive.

    Here are more questions I hope you can answer:

    1. It seems the LVDS will emerge on pins GPIO2 and GPIO3 (in "analog" mode).  

           1a.  Is this right? (GPIO2 and GPIO3).

            1b. Which of the two pins [GPIO2, GPIO3] has positive polarity for the LVDS diff pair?

            1c.  My interpretation of your "[I 1 Q 0]" notation is that there is only one LVDS diff pair and  I and Q will be time-multiplexed on it, alternating with a fixed 1 bit following each I bit and a fixed 0 bit following each Q bit.  Is this right?

            1d. The chip does not emit a corresponding LVDS source clock.  Instead, it is up to the user to come up with a 2*XOSC clock with proper phasing to clock the LVDS data into the downstream device.  Is this right?

            1e. The chip does not emit a separate sync to indicate where I and Q are in the stream.  Instead, the sync is to be inferred from the timing of the fixed 0 and 1 bits.

    2. Regarding taking the I and Q data after the channel filter.  It is my understanding that after the channel filter, the signals would have a multi-bit representation.  They would no longer be one-bit sigma-delta modulated.  So they would either come out the LVDS interface in an entirely different format, or perhaps you were referring to accessing registers CHFILT_Ix and CHFILT_Qx over the SPI.

    Regards,

    Tilde ~

  • 0 in reply to Tilde the Hun
    TI__Guru**** 317180 points
    1a) Yes
    1b) Have to double check
    1c) Yes, it's time multiplexed data.
    1d) Yes, I think we have used a FPGA with high enough clock to be able to oversample the data on the LVDS interface
    1e) yes

    2) They are possible to read out on the CHFILT_I/Q over SPI. You can output a pin (see table 10 in the UserGuide) that can used as an interrupt to the MCU (sample ready in the register)

    Reading out the data from the channel filter require less data processing that taking the data from the LVDS interface.
  • 0 in reply to TER
    Prodigy 30 points
    Ter,

    Which of the two pins [GPIO2, GPIO3] has positive polarity for the LVDS diff pair?

    Thank you