Other Parts Discussed in Thread: CC1310
Hello,
I am using proprietary mode on the CC1350. I am wanting to do a simple repetition code in a single packet to allow error correction if any bits are wrong. I have appended my RF studio settings at the end of this message. They are set to do DSSS at 62.5kbps.
My concern is that when the RSSI is near the edge of the receiver sensitivity my Sync word will have errors causing the packet to not be seen by the CC1350 reducing the effectiveness of my error correction repetition code. Is there a way to adjust the threshold of the Sync word to allow for some error so that there is more of a chance for the error correction to recover the packet? If so how can this be achieved?
Thanks,
Josh
//*********************************************************************************
// Generated by SmartRF Studio version 2.6.0 (build #8)
// Tested for SimpleLink SDK version: CC13x0 SDK 1.30.xx.xx
// Device: CC1350 Rev. 2.1 (Rev. B)
//
//*********************************************************************************
//*********************************************************************************
// Parameter summary
// Address: off
// Address0: 0xAA
// Address1: 0xBB
// Frequency: 915.00000 MHz
// Data Format: Serial mode disable
// Deviation: 25.000 kHz
// Packet Length Config: Variable
// Max Packet Length: 255
// Packet Length: 30
// RX Filter BW: 98 kHz
// Symbol Rate: 50.00000 kBaud
// Sync Word Length: 32 Bits
// TX Power: 14 dBm (requires define CCFG_FORCE_VDDR_HH = 1 in ccfg.c, see CC13xx/CC26xx Technical Reference Manual)
// Whitening: No whitening
#ifdef DEVICE_FAMILY
#undef DEVICE_FAMILY_PATH
#define DEVICE_FAMILY_PATH(x) <ti/devices/DEVICE_FAMILY/x>
#else
#error "You must define DEVICE_FAMILY at the project level as one of cc26x0, cc26x0r2, cc13x0, etc."
#endif
#include DEVICE_FAMILY_PATH(driverlib/rf_mailbox.h)
#include DEVICE_FAMILY_PATH(driverlib/rf_common_cmd.h)
#include DEVICE_FAMILY_PATH(driverlib/rf_prop_cmd.h)
#include <ti/drivers/rf/RF.h>
// #include DEVICE_FAMILY_PATH(rf_patches/rf_patch_cpe_genfsk.h)
// #include DEVICE_FAMILY_PATH(rf_patches/rf_patch_rfe_genfsk.h)
#include DEVICE_FAMILY_PATH(rf_patches/rf_patch_cpe_wb_dsss.h)
#include DEVICE_FAMILY_PATH(rf_patches/rf_patch_mce_wb_dsss.h)
#include DEVICE_FAMILY_PATH(rf_patches/rf_patch_rfe_wb_dsss.h)
#include "smartrf_settings.h"
RF_Mode RF_prop =
{
.rfMode = RF_MODE_PROPRIETARY_SUB_1,
.cpePatchFxn = &rf_patch_cpe_wb_dsss,
.mcePatchFxn = &rf_patch_mce_wb_dsss,
.rfePatchFxn = &rf_patch_rfe_wb_dsss,
};
// Overrides for CMD_PROP_RADIO_DIV_SETUP
static uint32_t pOverrides[] =
{
// override_use_patch_prop_genfsk.xml
// PHY: Use MCE ROM bank 4, RFE RAM patch
// MCE_RFE_OVERRIDE(0,4,0,1,0,0),
MCE_RFE_OVERRIDE(1, 0, 0, 1, 0, 0), // Apply MCE and RFE patches
// override_synth_prop_863_930_div5.xml
// Synth: Set recommended RTRIM to 7
HW_REG_OVERRIDE(0x4038,0x0037),
// Synth: Set Fref to 4 MHz
(uint32_t)0x000684A3,
// Synth: Configure fine calibration setting
HW_REG_OVERRIDE(0x4020,0x7F00),
// Synth: Configure fine calibration setting
HW_REG_OVERRIDE(0x4064,0x0040),
// Synth: Configure fine calibration setting
(uint32_t)0xB1070503,
// Synth: Configure fine calibration setting
(uint32_t)0x05330523,
// Synth: Set loop bandwidth after lock to 20 kHz
(uint32_t)0x0A480583,
// Synth: Set loop bandwidth after lock to 20 kHz
(uint32_t)0x7AB80603,
// Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
ADI_REG_OVERRIDE(1,4,0x9F),
// Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1)
ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
// Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering
(uint32_t)0x02010403,
// Synth: Configure extra PLL filtering
(uint32_t)0x00108463,
// Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us)
(uint32_t)0x04B00243,
// override_phy_rx_aaf_bw_0xd.xml
// Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
// override_phy_gfsk_rx.xml
// Rx: Set LNA bias current trim offset to 3
(uint32_t)0x00038883,
// Rx: Freeze RSSI on sync found event
HW_REG_OVERRIDE(0x6084,0x35F1),
// override_phy_gfsk_pa_ramp_agc_reflevel_0x1a.xml
// Tx: Configure PA ramping setting (0x41). Rx: Set AGC reference level to 0x1A.
// HW_REG_OVERRIDE(0x6088,0x411A),
HW_REG_OVERRIDE(0x6088,0x410E), // AGC reference level to 0x0E
// Tx: Configure PA ramping setting
HW_REG_OVERRIDE(0x608C,0x8213),
HW_REG_OVERRIDE(0x52AC,0x0B03), //DSSS = 4, K=4
HW_REG_OVERRIDE(0x5108,0x0048), //Correlator Threshold for Sync
// override_phy_rx_rssi_offset_5db.xml
// Rx: Set RSSI offset to adjust reported RSSI by +5 dB
(uint32_t)0x00FB88A3,
// TX power override
// Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8)
ADI_REG_OVERRIDE(0,12,0xF8),
(uint32_t)0xFFFFFFFF,
};
