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WL1837MOD: HCI_VS_Write_CODEC_Config Frame Sync Duty Cycle vs Frame Sync Edge

Part Number: WL1837MOD

For the BT VS commands, I'm trying to understand the difference between the following fields within the HCI_VS_Write_CODEC_Config command:

  • Frame Sync Edge (Rising/Falling)
  • Frame Sync Polarity (active high/active low)

So clearly one of these specifies whether the frame sync is active high (i.e. begins with the rising edge) or active low (begins with the falling edge).  Which one is it?  And what is the meaning of the other?

  • Hi Brad,

    Your query has been assigned to relevant experts. We will get back to you shortly.

    Best regards,
    Vihang
  • Hi Brad,

    The Frame Sync polarity specifies whether the frame sync is active high or active low. The Frame Sync Edge on the other hand indicates if the FSYNC line transitions will occur on the rising or falling edge of the bit clock(PCM clock).

    So,
    - The Frame Sync Polarity is used to determine whether the data is transferred during low or high state of the FSYNC.
    - The Frame Sync Edge is used to determine the FSYNC high->low or low->high transitions with respect to the PCM clock edge.

    Hope this helps clarify it.

    Best regards,
    VIhang
  • That's very clear for when the WL1837MOD is the master.  What about slave mode?  Is this a "don't care" or does it need to be configured to reflect how the pins are being driven?

  • When the WL8xx is the PCM slave, then the FSync Edge parameter defines the edge of the PCM clock that the WL18xx will sample the FSync signal.

    For example: If WL18xx is PCM slave and the master always asserts/deasserts the FSync on the falling edge, configure the WL18xx FSync edge as rising edge. That would mean that the WL18xx will Sample the FSync line for activity on every rising edge of the PCM clock. The Edge should be opposite to the other device's edge in order to avoid jitter.