/* Disable DSI */
ds90ub941_write_reg(ds90ub941, addr, 0x01, 0x08);
/* enable continuous clock mode */
ds90ub941_write_reg(ds90ub941, addr, 0x1E, 0x01);
ds90ub941_write_reg(ds90ub941, addr, 0x4F, 0x8c);
/*Enable Left/Right 3D processing to allow superframe splitting*/
ds90ub941_write_reg(ds90ub941, addr, 0x5B, 0x07);
ds90ub941_write_reg(ds90ub941, addr, 0x56, 0x00);
/* Set line size */
// Here is 1280 as default
ds90ub941_write_reg(ds90ub941, addr, 0x32, 0x00);
ds90ub941_write_reg(ds90ub941, addr, 0x33, 0x05);

/*Crop Port0 720p image*/
ds90ub941_write_reg(ds90ub941, addr, 0x1E, 0x1);
ds90ub941_write_reg(ds90ub941, addr, 0x36, 0x00); // set crop start X(LSB)
ds90ub941_write_reg(ds90ub941, addr, 0x37, 0x80); // set crop start X(MSB) and enable cropping
ds90ub941_write_reg(ds90ub941, addr, 0x38, 0xFF); // set crop stop x(LSB) 1279
ds90ub941_write_reg(ds90ub941, addr, 0x39, 0x04); // set crop stop x(MSB)
ds90ub941_write_reg(ds90ub941, addr, 0x3A, 0x00); // set crop start y(LSB)
ds90ub941_write_reg(ds90ub941, addr, 0x3B, 0x00); // set crop start y(MSB)
ds90ub941_write_reg(ds90ub941, addr, 0x3C, 0xCF); // set crop stop y(LSB) 719
ds90ub941_write_reg(ds90ub941, addr, 0x3D, 0x02); // set crop stop y(MSB)

/*Crop Port1 720p image*/
ds90ub941_write_reg(ds90ub941, addr, 0x1E, 0x2);
ds90ub941_write_reg(ds90ub941, addr, 0x36, 0x00); // set crop start X(LSB)
ds90ub941_write_reg(ds90ub941, addr, 0x37, 0x80); // set crop start X(MSB) and enable cropping
ds90ub941_write_reg(ds90ub941, addr, 0x38, 0xFF); // set crop stop x(LSB) 1279
ds90ub941_write_reg(ds90ub941, addr, 0x39, 0x04); // set crop stop x(MSB)
ds90ub941_write_reg(ds90ub941, addr, 0x3A, 0x00); // set crop start y(LSB)
ds90ub941_write_reg(ds90ub941, addr, 0x3B, 0x00); // set crop start y(MSB)
ds90ub941_write_reg(ds90ub941, addr, 0x3C, 0xCF); // set crop stop y(LSB) 719
ds90ub941_write_reg(ds90ub941, addr, 0x3D, 0x02); // set crop stop y(MSB)

/* Initialize internal DSI clock settings */
ds90ub941_write_reg(ds90ub941, addr, 0x40, 0x10);
ds90ub941_write_reg(ds90ub941, addr, 0x41, 0x86);
ds90ub941_write_reg(ds90ub941, addr, 0x42, 0x0A);
ds90ub941_write_reg(ds90ub941, addr, 0x41, 0x94);
ds90ub941_write_reg(ds90ub941, addr, 0x42, 0x0A);

/*Program TSKIP_CNT DSI parameter on DSI Port0*/


/* Enable DSI */
ds90ub941_write_reg(ds90ub941, addr, 0x01, 0x00);