{ 0x00, 0x01 },		// 01: 
									//    bit 7: E_EL Device identifivation. 0= CDCEL913 (1.8 V out)
									//    bit [6:4] RID Revision identification number (read-only)
									//    bit [3:0] VID Vendor identificatio nnumber (read-only) = 1
		{ 0x01, 0x01 },//0x00?		// 02: SLAVE_ADR[1:0] 01b Address bits A0 and A1 of the slavereceiveraddress0
		{ 0x02, 0xB4 },		// 03; 0xB4 = 0b1011.0100
									//    bit 7:	M1	1b	Clock source selection for output Y1:0-Inputclock / 1-PLL1clock
									//    bit 6: 	SPICON Operation mode selection for pin 12/13: 0=Serial programming interface SDA(pin 13) and SCL(pin 12)
									//    bit 5-4: Y1_ST1: Y1-State definition 11= Y1 enabled
									//    bit 3-2: Y1_ST0: Y0-State definition 01= Y0 disabled to 3-state
									//    bit 1-0: Pdiv1[9:8] 10-bitY1-output-divider Pdiv1: 00 = Divider reset and stand-by
		{ 0x03, 0x03 },		// 04
									//    bit Pdiv1[7:0] 0x01= div 1
		{ 0x04, 0x02 },		// 05 0x02 = 0b0000.0010 Y1_x State Selection
									//    bit 2: Y1_1:	1= State1(predefinedby Y1_ST1)
									//    bit 
		{ 0x05, 0x50 },		// 06 XCSEL: Crystal load capacitor selection
									//    0x50=20pF (bit[2:0] reserved)
		{ 0x06, 0x40 }, 		// 07 BCOUNT / EEWRITE 	0x0e = 0b0000.1110
									//    bit [7:1] 7-bit byte count (defines the number of bytes which will be sent from this device at the next BlockRead transfer);
									//		all bytes must be readout to finish the read cycle correctly.
									//    bit [0] EEWRITE  Initiate EEPROM write cycle -> 0= No EEPROM write cycle
		{ 16, 0x00 }, 		// 08 SSC1: PLL1 SSC selection -> 0=Spread Spectrum off
		{ 17, 0x00 }, 		// 09 SSC1: PLL1 -> 0=Spread Spectrum off
		{ 18, 0x00 }, 		// 10 SSC1: PLL1 -> 0=Spread Spectrum off
		{ 19, 0x00 }, 		// 11 FS1_x:PLL1frequencyselection
									//    all 0 -> predefined by PLL1_0 - multiplier/divider value 
		{ 20, 0x6d }, 		// 12 PLL Multiplexer 0xED = 0b1110.1101
									//    bit 7: MUX1 PLL1 multiplexer: 1-> PLL1 bypass
									//    bit 6: M2 Output Y2 multiplexer 1-> Pdiv2
									//    bit [5:4]: M3 Output Y3 multiplexer 10->
									//    bit [3:2]: Y2Y3_ST1 11-> Y2/Y3 enabled
									//    bit [1:0]: Y2Y3_ST0 01-> Y2/Y3 disabled to 3-State
		{ 21, 0x02 }, 		// 13 Y2Y3_x output state selection 0x02 = 0b0000.0010
									//    bit 2: 1= State1 (predefined by Y2Y3_ST1)  
		{ 22, 0x00 }, 		// 14 Pdiv2 1= div 1
		{ 23, 0x00 }, 		// 15 Pdiv3 1= div 1
		{ 24, 0xE3 }, 		// 16 
									//    bit [7:0] PLL1_0N [11:4]
		{ 25, 0x8E }, 		// 17 
									//    bit [7:4] PLL1_0N [3:0]
									//    bit [3:0] PLL1_0R [8:5]
		{ 26, 0x03 }, 		// 18 
									//    bit [7:3] PLL1_0R [4:0]
									//    bit [2:0] PLL1_0Q [5:3]
/*27*/{ 27, 0x8B }, 		// 19 
									//    bit [7:5] PLL1_0Q [2:0]
									//    bit [4:2] PLL1_0P [2:0]
									//    bit [1:0]  fVCO1_0 range selection: 00 - fVCO1_1 < 125 MHz
		{ 28, 0xE3 }, 		// 20 
									//    bit [7:0] PLL1_1N [11:4]
		{ 29, 0x8E }, 		// 21 
									//    bit [7:4] PLL1_1N [3:0]
									//    bit [3:0] PLL1_1R [8:5]
		{ 30, 0x03 }, 		// 22 PLL1_1
									//    bit [7:3] PLL1_1R [4:0]
									//    bit [2:0] PLL1_1Q [5:3]
/*31*/{ 31, 0x88 } 		// 23
									//    bit [7:5] PLL1_1Q [2:0]
									//    bit [4:2] PLL1_1P [2:0]
									//    bit [1:0]  fVCO1_1 range selection: 00 - fVCO1_1 < 125 MHz
	};