Address 0x18 is for channel A
Address 0x19 is for channel B

Write 0x18 0x1E 0x0000 0x8610 --> Set GLOBAL_RESET (bit 15)
Write 0x18 0x1E 0x0000 0x3E30 --> Reset GLOBAL_RESET, Set GLOBAL_WRITE (bit 11), Set PRTAD0_PIN_EN (bit 5)

Write 0x18 0x1E 0x0001 0x8B00 --> Set POWERDOWN (bit 15)
Write 0x18 0x01 0x0096 0x0000 --> Reset LT_TRAINING_ENABLE (bit 1)
Write 0x18 0x07 0x0000 0x2000 --> Reset AN_ENABLE (bit 12)

Write 0x18 0x01 0x9000 0x024D --> TI_RESERVED_CONTROL register 
Write 0x18 0x1E 0x8101 0x0004 --> Enable DEFAULT_TX_TRIGGER
Write 0x18 0x1E 0x8100 0x0004 --> Trigger loading default HS TX setting values
Write 0x18 0x1E 0x8100 0x0000 --> Trigger loading default HS TX setting values
Write 0x18 0x01 0x9001 0x0200 --> Link train: Auto search, autotrain enabled

Write 0x19 0x1E 0x0001 0x0B00 --> Reset POWERDOWN (bit 15)

Write 0x18 0x1E 0x0000 0x3630 --> Reset GLOBAL_WRITE (bit 11)
Write 0x18 0x1E 0x0017 0x3000 --> Set DST_PIN_SW_EN (bit 12) of channel-A DST_CONTROL_1
Write 0x19 0x1E 0x0017 0x3A00 --> Set DST_PIN_SW_EN (bit 12), Set DST_PIN_SW_SRC_0 (bit [9:8]) = 10 , DST_PIN_SW_SRC_1 (bit [11:10]) = 10 of channel-B DST_CONTROL_1
Write 0x18 0x1E 0x0019 0x3700 --> Set DST_PIN_SW_SRC_0 (bit 12), Set DSR_PIN_SW_SRC_0 (bit [9:8]) = 11, DSR_PIN_SW_SRC_1 (bit [11:10]) = 01 of channel-A DSR_CONTROL_1
Write 0x18 0x07 0x0000 0x3000 --> Set AN_ENABLE (bit 12) of channel-A AN_CONTROL
Write 0x19 0x07 0x0000 0x3000 --> Set AN_ENABLE (bit 12) of channel-B AN_CONTROL
Write 0x18 0x01 0x0096 0x0002 --> Set LT_TRAINING_ENABLE (bit 1) of channel-A LT_TRAIN_CONTROL
Write 0x19 0x01 0x0096 0x0002 --> Set LT_TRAINING_ENABLE (bit 1) of channel-B LT_TRAIN_CONTROL

Write 0x18 0x1E 0x000E 0x000E --> Set DATAPATH_RESET (bit 3), TXFIFO_RESET (bit 2), RXFIFO_RESET (bit 1) of channel-A RESET_CONTROL
Write 0x19 0x1E 0x000E 0x000E --> Set DATAPATH_RESET (bit 3), TXFIFO_RESET (bit 2), RXFIFO_RESET (bit 1) of channel-B RESET_CONTROL

Workaround to bringup LS side and HS side linkup and data switch selection
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If SW detectes Switch-A is Active (PRTAD0 = 1), 
Write 0x19 0x01 0x0096 0x0000 --> Reset LT_TRAINING_ENABLE (bit 1) of Channel-B LT_TRAIN_CONTROL
Write 0x19 0x07 0x0000 0x2000 --> Reset AN_ENABLE (bit 12) of Channel-B AN_CONTROL
Write 0x18 0x07 0x0000 0x3200 --> Set AN_RESTART (bit 9) of channel-A AN_CONTROL
Write 0x18 0x01 0x0096 0x0002 --> Set LT_TRAINING_ENABLE (bit 1) of Channel-A LT_TRAIN_CONTROL
Write 0x18 0x1E 0x000E 0x000E --> Set DATAPATH_RESET (bit 3), TXFIFO_RESET (bit 2), RXFIFO_RESET (bit 1) of channel-A RESET_CONTROL
Write 0x19 0x1E 0x000E 0x000E --> Set DATAPATH_RESET (bit 3), TXFIFO_RESET (bit 2), RXFIFO_RESET (bit 1) of channel-B RESET_CONTROL

If SW detects Switch-B is Active (PRTAD0 = 0), 
Write 0x18 0x01 0x0096 0x0000 --> Reset LT_TRAINING_ENABLE (bit 1) of Channel-A LT_TRAIN_CONTROL
Write 0x18 0x07 0x0000 0x2000 --> Reset AN_ENABLE (bit 12) of Channel-A AN_CONTROL
Write 0x19 0x07 0x0000 0x3200 --> Set AN_RESTART (bit 9) of channel-B AN_CONTROL
Write 0x19 0x01 0x0096 0x0002 --> Set LT_TRAINING_ENABLE (bit 1) of Channel-B LT_TRAIN_CONTROL
Write 0x18 0x1E 0x000E 0x000E --> Set DATAPATH_RESET (bit 3), TXFIFO_RESET (bit 2), RXFIFO_RESET (bit 1) of channel-A RESET_CONTROL
Write 0x19 0x1E 0x000E 0x000E --> Set DATAPATH_RESET (bit 3), TXFIFO_RESET (bit 2), RXFIFO_RESET (bit 1) of channel-B RESET_CONTROL