status = ak_gmac_read_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, PHY_ID_HI_REG, &data_id1);
	if(status) { 
		printk("phy read phy id1 waiting Error,data=0x%x\n", data_id1);  
		goto err_phy_reg;
	}

	status = ak_gmac_read_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, PHY_ID_LOW_REG, &data_id2);
	if(status) { 
		printk("phy read phy id2 waiting Error,data=0x%x\n", data_id2);  
		goto err_phy_reg;
	}


	else if(data_id1 == 0x2000 && ((data_id2 == 0xa140) || (data_id2 == 0xa130) || (data_id2 == 0xa110)) ) {  /* dp83825 and dp83826 initialization*/
        printk("cdh:id 0xa140 or 0xa130 or 0xa110 set!\n");

		/* RMII Reference Clock Selec: RMII Reference Clock Selec */
		data_ctl = 0;
        ak_gmac_read_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x17, &data_ctl);
	 	data_ctl |= (1<<7);
	 	ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x17, data_ctl);

#if 1
		data_ctl = 0;
		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0D, 0x1F);
		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0E, 0x0468);
		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0D, 0x401F);
		ak_gmac_read_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0E, &data_ctl);

		printk("xzj 0x0468 reg val:0x%x\n", data_ctl);
		data_ctl |= 0x18;

		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0D, 0x1F);
		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0E, 0x0468);
		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0D, 0x401F);
		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0E, data_ctl);

		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0D, 0x1F);
		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0E, 0x0468);
		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0D, 0x401F);
		ak_gmac_read_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, 0x0E, &data_ctl);

		printk("xzj read back 0x0468 reg val:0x%x\n", data_ctl);
#endif

		/* Enable Auto-Negotiation */
		data_ctl = 0;
		ak_gmac_read_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, &data_ctl);
		//data_ctl |= 0x1000;
		data_ctl |= 0x1020;
		ak_gmac_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, data_ctl);
    }