superframe image size outputted by SoC is :
    uVisWidth        = '1920'
    uHsyncFrontPorch = '50'
    uHsyncWidth      = '50'
    uHsyncBackPorch  = '50'
    uVisHeight       = '720'
    uVsyncFrontPorch = '50'
    uVsyncWidth      = '50'
    uVsyncBackPorch  = '50'
	
reg dump:
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 18 00 00 9a 00 00 58 58 5c 01 41 00 07 30 00 00    ?..?..XX\?A.?0..
10: 00 00 00 9f 00 00 fe 1e 7f 7f 01 00 04 00 04 00    ...?..?????.?.?.
20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
30: 00 09 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
40: 10 94 00 00 00 00 00 00 00 00 00 00 00 00 00 8c    ??.............?
50: 16 00 00 00 02 10 80 02 00 00 f9 07 07 06 44 35    ?...????..????D5
60: 22 02 00 00 15 00 0d 32 00 00 00 00 00 00 20 00    "?..?.?2...... .
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7c 00    ..............|.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 82 00 38 00 00 64 40 00 00 00 00 02 ff 00    ..?.8..d@....??.
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 82 00 28 08 00 00 00 00 00 00 00 02 00 00    ..?.(?.......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........	

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 58 04 00 f0 fe 1e 00 18 00 00 00 00 00 00 00 00    X?.???.?........
10: 00 00 00 00 00 00 00 00 00 01 00 00 23 10 00 00    .........?..#?..
20: 00 00 40 30 08 00 83 84 01 00 00 00 00 00 00 00    ..@0?.???.......
30: 00 00 90 25 01 00 00 ac 00 00 00 07 20 e0 23 00    ..?%?..?...? ?#.
40: 43 03 03 00 60 88 00 00 0f 80 00 08 00 00 63 00    C??.`?..??.?..c.
50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00    ??.??....?  ....
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00    ....?...........
70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 8c 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........

reg config:
 0x01,0x08, // Reset
 0x01,0x02, // Reset

 0x5B,0x07, //Set 941AS to Splitter mode
 0x56,0x80, //Set 941AS to Splitter mode

 0x1E,0x01, //Select FPD-Link III Port 0
 0x66,0x1A,
 0x67,0x01, //M=1
 0x66,0x03,
 0x67,0x02, //N=2

 0x66,0x04,
 0x67,0x0b, //least 8 bit of Total Horizontal frame size
 0x66,0x05,
 0x67,0x64, //Least 4 bit TV + Most 4 bit TH
 0x66,0x06,
 0x67,0x36, //Most 8 bit of Total Vertical frame size

 0x66,0x07,
 0x67,0xc0, //least 8 bit of active Horizontal frame size
 0x66,0x08,
 0x67,0x03, //Least 4 bit AV + Most 4 bit AH
 0x66,0x09,
 0x67,0x2D, //Most 8 bit of active Vertical frame size

 0x66,0x0A,
 0x67,0x16, //Horizontal Sync Width
 0x66,0x0B,
 0x67,0x32, //Vertical Sync Width
 0x66,0x0C,
 0x67,0x16, //Horizontal back porch
 0x66,0x0D,
 0x67,0x32, //Vertical back porch
 0x65,0x00, //using internal timing and internal clock
 0x64,0x15, //enable PG/color bars

 0x1E,0x02, //Select FPD-Link III Port 0
 0x66,0x1A,
 0x67,0x01, //M=1
 0x66,0x03,
 0x67,0x02, //N=2

 0x66,0x04,
 0x67,0x0b, //least 8 bit of Total Horizontal frame size
 0x66,0x05,
 0x67,0x64, //Least 4 bit TV + Most 4 bit TH
 0x66,0x06,
 0x67,0x36, //Most 8 bit of Total Vertical frame size

 0x66,0x07,
 0x67,0xc0, //least 8 bit of active Horizontal frame size
 0x66,0x08,
 0x67,0x03, //Least 4 bit AV + Most 4 bit AH
 0x66,0x09,
 0x67,0x2D, //Most 8 bit of active Vertical frame size

 0x66,0x0A,
 0x67,0x16, //Horizontal Sync Width
 0x66,0x0B,
 0x67,0x32, //Vertical Sync Width
 0x66,0x0C,
 0x67,0x16, //Horizontal back porch
 0x66,0x0D,
 0x67,0x32, //Vertical back porch
 0x65,0x00, //using internal timing and internal clock
 0x64,0x31, //enable PG/color bars

 0x01,0x00, //enable DSI

 0x1E,0x01, //Select FPD-Link III Port 0
 0x07,0x58, //0x07,0x58
 0x08,0x5C, //0x08,0x5c
 0x03,0x9A, //0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0

 0x1E,0x02, //Select FPD-Link III Port 1 0x1E,0x02, 
 0x07,0x58, //0x07,0x58
 0x08,0x5E, //0x08,0x5E
 0x03,0x9A, //0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
 0x1E,0x04, //0x1E,0x04