* OPA388 - Rev. A * Created by Ian Williams; December 07, 2016 * Created with Green-Williams-Lis Op Amp Macro-model Architecture * Copyright 2016 by Texas Instruments Corporation ****************************************************** * MACRO-MODEL SIMULATED PARAMETERS: ****************************************************** * OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol) * UNITY GAIN BANDWIDTH (GBW) * INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR) * POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR) * DIFFERENTIAL INPUT IMPEDANCE (Zid) * COMMON-MODE INPUT IMPEDANCE (Zic) * OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo) * OUTPUT CURRENT THROUGH THE SUPPLY (Iout) * INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en) * INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in) * OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo) * SHORT-CIRCUIT OUTPUT CURRENT (Isc) * QUIESCENT CURRENT (Iq) * SETTLING TIME VS. CAPACITIVE LOAD (ts) * SLEW RATE (SR) * SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD * LARGE SIGNAL RESPONSE * OVERLOAD RECOVERY TIME (tor) * INPUT BIAS CURRENT (Ib) * INPUT OFFSET CURRENT (Ios) * INPUT OFFSET VOLTAGE (Vos) * INPUT COMMON-MODE VOLTAGE RANGE (Vcm) * INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm) * INPUT/OUTPUT ESD CELLS (ESDin, ESDout) ****************************************************** .subckt OPA388 IN+ IN- VCC VEE OUT ****************************************************** * MODEL DEFINITIONS: .model BB_SW VSWITCH(Ron=50 Roff=1e12 Von=700e-3 Voff=0) .model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=500e-3 Voff=100e-3) .model OL_SW VSWITCH(Ron=1e-3 Roff=1e12 Von=900e-3 Voff=800e-3) .model OR_SW VSWITCH(Ron=10e-3 Roff=1e12 Von=1e-3 Voff=0) .model R_NOISELESS RES(T_ABS=-273.15) ****************************************************** V_OS N036 N046 -240.202e-9 R1 N039 N037 R_NOISELESS 1e-3 R2 N055 ESDn R_NOISELESS 1e-3 R3 N083 0 R_NOISELESS 1e12 C1 N083 0 1 R4 VCC_B N082 R_NOISELESS 1e-3 C2 N082 0 1e-15 C3 N084 0 1e-15 R5 N084 VEE_B R_NOISELESS 1e-3 G1 N039 N040 N005 N012 1e-3 R6 MID N051 R_NOISELESS 1e12 VCM_MIN N054 VEE_B -0.1 R7 N054 MID R_NOISELESS 1e12 VCM_MAX N051 VCC_B +0.1 XVCM_CLAMP N040 MID N047 MID N051 N054 VCCS_EXT_LIM R8 N047 MID R_NOISELESS 1 C4 N048 MID 1e-15 R9 N047 N048 R_NOISELESS 1e-3 V4 N076 OUT 0 R10 MID N056 R_NOISELESS 1e12 R11 MID N057 R_NOISELESS 1e12 XIQ+ VIMON MID VCC MID VCCS_LIM_IQ XIQ- MID VIMON MID VEE VCCS_LIM_IQ R12 VCC_B N013 R_NOISELESS 1e3 R13 N026 VEE_B R_NOISELESS 1e3 XCLAWp VIMON MID N013 VCC_B VCCS_LIM_CLAWp XCLAWn MID VIMON VEE_B N026 VCCS_LIM_CLAWn R14 VEE_CLP MID R_NOISELESS 1e3 R15 MID VCC_CLP R_NOISELESS 1e3 R16 N014 N013 R_NOISELESS 1e-3 R17 N027 N026 R_NOISELESS 1e-3 C5 MID N014 1e-15 C6 N027 MID 1e-15 R18 VOUT_S N057 R_NOISELESS 100 C7 VOUT_S MID 1e-9 G2 MID VCC_CLP N014 MID 1e-3 G3 MID VEE_CLP N027 MID 1e-3 XCL_AMP N009 N038 VIMON MID N017 N024 CLAMP_AMP_LO V_ISCp N009 MID 60 V_ISCn N038 MID -60 XOL_SENSE MID N044 N043 N053 OL_SENSE R19 N038 MID R_NOISELESS 1e12 R20 N024 MID R_NOISELESS 1 C8 N025 MID 1e-15 R21 MID N017 R_NOISELESS 1 R22 MID N009 R_NOISELESS 1e12 C9 MID N018 1e-15 XCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID N015 N022 CLAMP_AMP_LO R23 VEE_CLP MID R_NOISELESS 1e12 R24 N022 MID R_NOISELESS 1 C10 N023 MID 1e-15 R25 MID N015 R_NOISELESS 1 R26 MID VCC_CLP R_NOISELESS 1e12 C11 MID N016 1e-15 XCL_SRC N018 N025 CL_CLAMP MID VCCS_LIM_4 XCLAW_SRC N016 N023 CLAW_CLAMP MID VCCS_LIM_3 R27 N015 N016 R_NOISELESS 1e-3 R28 N023 N022 R_NOISELESS 1e-3 R29 N017 N018 R_NOISELESS 1e-3 R30 N025 N024 R_NOISELESS 1e-3 R31 N044 MID R_NOISELESS 1 R32 N044 SW_OL R_NOISELESS 100 C12 SW_OL MID 1e-12 R33 VIMON N056 R_NOISELESS 100 C13 VIMON MID 1e-9 C_DIFF ESDp ESDn 2e-12 C_CMn ESDn MID 4.5e-12 C_CMp MID ESDp 4.5e-12 I_Q VCC VEE 1.9e-3 I_B N040 MID 30e-12 I_OS N055 MID -30e-12 R34 IN+ ESDp R_NOISELESS 10e-3 R35 IN- ESDn R_NOISELESS 10e-3 R36 N034 MID R_NOISELESS 1 R37 N041 MID R_NOISELESS 1e12 R38 MID N020 R_NOISELESS 1 R39 MID N010 R_NOISELESS 1e12 XGR_AMP N010 N041 N019 MID N020 N034 CLAMP_AMP_HI XGR_SRC N021 N035 CLAMP MID VCCS_LIM_GR C17 MID N021 1e-15 C18 N035 MID 1e-15 V_GRn N041 MID -17 V_GRp N010 MID 17 R40 N020 N021 R_NOISELESS 1e-3 R41 N035 N034 R_NOISELESS 1e-3 R42 VSENSE N019 R_NOISELESS 1e-3 C19 MID N019 1e-15 R43 MID VSENSE R_NOISELESS 1e3 G5 N036 N037 N008 MID 1e-3 G8 MID CLAW_CLAMP N077 MID 1e-3 R45 MID CLAW_CLAMP R_NOISELESS 1e3 G9 MID CL_CLAMP CLAW_CLAMP MID 1e-3 R46 MID CL_CLAMP R_NOISELESS 1e3 R47 N062 VCLP R_NOISELESS 100 C24 MID VCLP 1e-12 E4 N062 MID CL_CLAMP MID 1 E5 N057 MID OUT MID 1 H1 N056 MID V4 1e3 S1 N059 N058 SW_OL MID OL_SW R52 MID ESDp R_NOISELESS 1e12 R53 ESDn MID R_NOISELESS 1e12 R58 N037 N036 R_NOISELESS 1e3 R59 N082 N083 R_NOISELESS 1e6 R60 N083 N084 R_NOISELESS 1e6 R67 N040 N039 R_NOISELESS 1e3 G15 MID VSENSE CLAMP MID 1e-3 V_ORp N033 VCLP 10.5 V_ORn N028 VCLP -10.5 V11 N030 N029 0 V12 N031 N032 0 H3 N042 MID V12 10 S6 VCC OUT OUT VCC ESD_SW S7 OUT VEE VEE OUT ESD_SW E1 MID 0 N083 0 1 G16 0 VCC_B VCC 0 1 G17 0 VEE_B VEE 0 1 R88 VCC_B 0 R_NOISELESS 1 R89 VEE_B 0 R_NOISELESS 1 S8 N031 CLAMP CLAMP N031 OR_SW S9 CLAMP N030 N030 CLAMP OR_SW Xi_nn ESDn MID FEMT Xi_np N046 MID FEMT XVCCS_LIMIT_1 N048 N055 MID N049 VCCS_LIM_1 XVCCS_LIMIT_2 N049 MID MID CLAMP VCCS_LIM_2 R44 N049 MID R_NOISELESS 1e6 R68 CLAMP MID R_NOISELESS 1e6 G7 MID N050 VSENSE MID 1e-6 R69 N050 MID R_NOISELESS 1e6 G10 MID N029 N028 MID 1 R73 N029 MID R_NOISELESS 1 G11 MID N032 N033 MID 1 R74 N032 MID R_NOISELESS 1 H2 N052 MID V11 -10 Xe_n N046 N045 VNSE R51 N045 ESDp R_NOISELESS 1e-3 S2 VCC ESDn ESDn VCC ESD_SW S3 VCC ESDp ESDp VCC ESD_SW S4 ESDn VEE VEE ESDn ESD_SW S5 ESDp VEE VEE ESDp ESD_SW R71 N043 N042 R_NOISELESS 100 R72 N053 N052 R_NOISELESS 100 C27 N043 MID 1e-12 C28 N053 MID 1e-12 Rx N076 N075 R_NOISELESS 17.5e3 Rdummy N076 MID R_NOISELESS 1.75e3 G30 MID N058 CL_CLAMP N076 237.45e3 Rdc3 N058 MID R_NOISELESS 1 R110 N058 N059 R_NOISELESS 1e4 R111 N059 MID R_NOISELESS 9090.91 G31 MID N063 N059 MID 2.1 C41 N059 N058 3.98e-5 R112 N063 MID R_NOISELESS 1 R113 N063 N064 R_NOISELESS 62.73e3 R114 N064 N078 R_NOISELESS 1e4 C42 MID N078 7.96e-9 R115 N067 MID R_NOISELESS 1 R116 N069 N070 R_NOISELESS 1e4 R117 N070 MID R_NOISELESS 3.61e3 G32 MID N071 N070 MID 3.77 C43 N070 N069 4.08e-11 R118 N071 MID R_NOISELESS 1 R119 N065 MID R_NOISELESS 1 R120 N065 N066 R_NOISELESS 1.9e5 R121 N066 N079 R_NOISELESS 1e4 C44 MID N079 7.96e-10 R122 N069 MID R_NOISELESS 1 R123 N067 N068 R_NOISELESS 7.7e5 R124 N068 N080 R_NOISELESS 1e4 C45 MID N080 4.08e-11 R125 N073 N074 R_NOISELESS 1e4 R126 N074 MID R_NOISELESS 8 C46 N074 N073 2e-13 R127 N075 MID R_NOISELESS 1 R128 N073 MID R_NOISELESS 1 R129 N071 N072 R_NOISELESS 1e4 R130 N072 N081 R_NOISELESS 1e4 C47 MID N081 5.3e-13 G33 MID N065 N064 MID 1 G34 MID N067 N066 MID 1 G35 MID N069 N068 MID 1 G36 MID N073 N072 MID 1 XVCCS_LIM_ZO N074 MID MID N075 VCCS_LIM_ZO Rdc1 N060 MID R_NOISELESS 1 R61 N060 N061 R_NOISELESS 1e4 R62 N061 MID R_NOISELESS 11.11e3 G13 MID N077 N061 MID 1.9e-3 C21 N061 N060 1.59e-12 R63 N077 MID R_NOISELESS 1e3 G18 MID N060 N050 MID 1 C23 CLAMP MID 4.57e-7 C25 N050 MID 1.59e-15 C20 N003 N004 1.105e-12 R70 N003 MID R_NOISELESS 98.728e3 R75 N003 N004 R_NOISELESS 1e8 G_adjust1 MID N004 VCC_B MID 101.4e-6 Rsrc8 N004 MID R_NOISELESS 1 G20 MID N002 MID N003 1 Rsrc9 N002 MID R_NOISELESS 1 C22 N001 N002 1.105e-12 R76 N001 N002 R_NOISELESS 1e8 R77 N001 MID R_NOISELESS 98.728e3 G21 MID N005 MID N001 1014 Rsrc10 N005 MID R_NOISELESS 1 C15 N012 N011 1.516e-9 R54 N012 MID R_NOISELESS 61.76 R55 N012 N011 R_NOISELESS 1e8 G12 MID N011 VEE_B MID 162e-3 Rsrc2 N011 MID R_NOISELESS 1 C14 N007 N006 1.4e-13 R65 N007 MID R_NOISELESS 357.5e3 R66 N007 N006 R_NOISELESS 1e8 G_adjust2 MID N006 ESDp MID 2.8e-5 Rsrc1 N006 MID R_NOISELESS 1 G6 MID N008 MID N007 1 Rsrc3 N008 MID R_NOISELESS 1 .ends OPA388 * .subckt CLAMP_AMP_HI VC+ VC- VIN COM VO+ VO- .param G=10 GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)} GVo- COM Vo- Value = {IF(V(VIN,COM)10e-3 | V(4,1)>10e-3),1,0)} .ends OL_SENSE * .subckt FEMT 1 2 .param FLWF=1e-2 .param GLFF=0.151 .param RNVF=11840 .model DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0e-16 I1 0 7 10e-3 I2 0 8 10e-3 D1 7 0 DVNF D2 8 0 DVNF E1 3 6 7 8 {GLFF} R1 3 0 1e9 R2 3 0 1e9 R3 3 6 1e9 E2 6 4 5 0 10 R4 5 0 {RNVF} R5 5 0 {RNVF} R6 3 4 1e9 R7 4 0 1e9 G1 1 2 3 4 1e-6 .ends FEMT * .subckt VCCS_EXT_LIM VIN+ VIN- IOUT- IOUT+ VP+ VP- .param Gain = 1 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))} .ends VCCS_EXT_LIM * .subckt VCCS_LIM_3 VC+ VC- IOUT+ IOUT- .param Gain = 1 .param Ipos = 34e-3 .param Ineg = -34e-3 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)} .ends VCCS_LIM_3 * .subckt VCCS_LIM_4 VC+ VC- IOUT+ IOUT- .param Gain = 1 .param Ipos = 68e-3 .param Ineg = -68e-3 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)} .ends VCCS_LIM_4 * .subckt VCCS_LIM_CLAWp VC+ VC- IOUT+ IOUT- G1 IOUT+ IOUT- TABLE {abs(V(VC+,VC-))} = +(0, 2e-5) +(10, 1.2e-4 ) +(22, 2.6e-4) +(45, 6.5e-4) +(53, 8.8e-4) +(60, 1.24e-3) +(63, 1.53e-3) +(66, 2.55e-3) .ends VCCS_LIM_CLAWp * .subckt VCCS_LIM_CLAWn VC+ VC- IOUT+ IOUT- G1 IOUT+ IOUT- TABLE {abs(V(VC+,VC-))} = +(0, 2e-5) +(11, 3e-4) +(87, 2.75e-3) .ends VCCS_LIM_CLAWn * .subckt VCCS_LIM_IQ VC+ VC- IOUT+ IOUT- .param Gain = 1e-3 G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,Gain*V(VC+,VC-) )} .ends VCCS_LIM_IQ * .subckt VNSE 1 2 .param FLW=1e-3 .param GLF=1.085e-3 .param RNV=59.6854 .model DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16 I1 0 7 10E-3 I2 0 8 10E-3 D1 7 0 DVN D2 8 0 DVN E1 3 6 7 8 {GLF} R1 3 0 1E9 R2 3 0 1E9 R3 3 6 1E9 E2 6 4 5 0 10 R4 5 0 {RNV} R5 5 0 {RNV} R6 3 4 1E9 R7 4 0 1E9 E3 1 2 3 4 1 .ends VNSE * .subckt CLAMP_AMP_LO VC+ VC- VIN COM VO+ VO- .param G=1 GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)} GVo- COM Vo- Value = {IF(V(VIN,COM)