###Start 20240929 15:04:43 ReadyCheck_NAN###
###Start 20240929 15:04:43 Barcode_10###
###Start 20240929 15:04:44 AirCylinder_ON###
###Start 20240929 15:04:46 PowerON_###
###Start 20240929 15:04:47 DaleyTime_5###
###Start 20240929 15:04:52 UBoot_OPT_1###
20240929 15:04:52 "C:\FCT\Data\BurningFile\850-000407_3.0\DSP\OPT\dslite-C28xx_CPU1.bat"
20240929 15:05:14 Executing default command:
> dslite --mode flash -c user_files/configs/f28p659dk8-q1.ccxml -l user_files/settings/generated.ufsettings -s VerifyAfterProgramLoad="No verification" -e -f -v "user_files/images/dcsm_security_tool_NT3(OTP).out"  

DSLite version 12.7.0.3382
Configuring Debugger (may take a few minutes on first launch)...
	Initializing Register Database...
	Initializing: IcePick_C_0
	Executing Startup Scripts: IcePick_C_0
	Initializing: C28xx_CPU1
	Executing Startup Scripts: C28xx_CPU1
	Initializing: CPU1_CLA1
	Executing Startup Scripts: CPU1_CLA1
	Initializing: C28xx_CPU2
	Executing Startup Scripts: C28xx_CPU2
	Initializing: JLM
	Executing Startup Scripts: JLM
Connecting...
C28xx_CPU1: GEL Output: 
Memory Map Initialization Complete
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
info: C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after the selected CPU1/CPU2 flash banks executable are programmed.
info: C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, and CPU2 Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 200MHz using INTOSC as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
info: C28xx_CPU1: Before doing any flash operations using the flash plugin, (a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI. (b) Please select the flash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
Loading Program: user_files/images/dcsm_security_tool_NT3(OTP).out
	Preparing ... 
	.data: 0 of 128 at 0x78000
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
info: C28xx_CPU1: GSxMSEL register configured correctly
info: C28xx_CPU1: BankMuxSel register configured correctly
Erasing Flash
	Erasing Bank 0
	Erasing Bank 1: 20%
	Erasing Bank 2: 40%
	Erasing Bank 3: 60%
	Erasing Bank 4: 80%
	.text: 0 of 4 at 0x80000: 1%
	.data: 0 of 936 at 0x80008: 1%
	.text: 0 of 470 at 0x801e0: 15%
	.text: 0 of 5150 at 0x802d0: 22%
	.data: 0 of 36 at 0x80ce0: 99%
	Finished: 99%
	Setting PC to entry point.: 99%
Verifying Program: user_files/images/dcsm_security_tool_NT3(OTP).out
	Preparing ... 
	.data: 0 of 128 at 0x78000
error: C28xx_CPU1: File Loader: Verification failed: Values at address 0x078000@Program do not match Please verify target memory and memory map.
	Finished