//############################################################################# // // FILE: F2837xD_FPU_CFFT_lnk.cmd // // TITLE: Linker Command File for FPU library examples that run // on the 2837x platform // // This file includes all RAM and FLASH blocks present on the // 2837x and depending on the active build configuration(RAM or FLASH) // the appropriate sections will either be loaded into RAM or FLASH // blocks // //############################################################################# // $TI Release: C28x Floating Point Unit Library V2.03.00.00 $ // $Release Date: May 26, 2020 $ // $Copyright: Copyright (C) 2018 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //############################################################################# // NOTES: // 1. In addition to this memory linker command file, add the header linker // command file directly to the project. The header linker command file is // required to link the peripheral structures to the proper locations within // the memory map. // // The header linker files are found in // c2000\C2000Ware_X_XX_XX_XX\device_support\f2837x(d/s)\headers\cmd // // For BIOS applications add: F2837x(D/S)_Headers_BIOS_cpuX.cmd // For nonBIOS applications add: F2837x(D/S)_Headers_nonBIOS_cpuX.cmd // // 2. On reset all RAMGSx blocks are under the mastership of CPU1. The user // must configure the appropriate control registers to transfer mastership // of a RAMGSx block over to CPU2 // // 3. Memory blocks on F2837x are uniform (ie same physical memory) in both // PAGE 0 and PAGE 1. That is the same memory region should not be defined // for both PAGE 0 and PAGE 1. Doing so will result in corruption of program // and/or data. // // Contiguous SARAM memory blocks can be combined if required to create a // larger memory block. // //############################################################################# // The following definitions will help to align the input buffer.For the complex FFT // of size N, the input buffer must be aligned to a 4N word boundary. For a real FFT // of size N, the input buffer must be aligned to a 2N word boundary. The user may define // the macro either in the linker command file, as shown here, or // through the project properties under, // C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define --define CFFT_ALIGNMENT=512 #if !defined(CFFT_ALIGNMENT) #error define CFFT_ALIGNMENT under C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define #endif MEMORY { PAGE 0 : /* BEGIN is used for the "boot to SARAM" bootloader mode */ #if defined(RAM) BEGIN : origin = 0x000000, length = 0x000002 #elif defined(FLASH) BEGIN : origin = 0x080000, length = 0x000002 #endif RAMGS04 : origin = 0x00C000, length = 0x005000 RESET : origin = 0x3FFFC0, length = 0x000002 FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ PAGE 1 : BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ RAMM0 : origin = 0x000122, length = 0x0002DE RAMM1 : origin = 0x000400, length = 0x000400 RAMD01 : origin = 0x00B000, length = 0x001000 RAMLS012345 : origin = 0x008000, length = 0x003000 RAMGS515 : origin = 0x011000, length = 0x00B000 FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ } SECTIONS { codestart : > BEGIN, PAGE = 0 #if defined(RAM) .TI.ramfunc : > RAMGS04, PAGE = 0 .text : > RAMGS04, PAGE = 0 .cinit : > RAMGS04, PAGE = 0 .pinit : > RAMGS04, PAGE = 0 .switch : > RAMGS04, PAGE = 0 .econst : > RAMLS012345, PAGE = 1 //FFT Table FPUfftTables : > RAMLS012345, PAGE = 1 FPUmathTables : > RAMLS012345, PAGE = 1 #elif defined(FLASH) .TI.ramfunc : { *(.TI.ramfunc) c28x_fpu_dsp_library_coff.lib(.text) //coffのライブラリを選択しないと処理速度が遅い c28x_fpu_dsp_library_coff.lib(.text) c28x_fpu_dsp_library_coff.lib(.text) //c28x_fpu_dsp_library_coff.lib(.text) //c28x_fpu_dsp_library_coff.lib(.text) //c28x_fpu_dsp_library_coff.lib(.text) } LOAD = FLASHC, RUN = RAMGS04, RUN_START(_RamfuncsRunStart), LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), PAGE = 0 .text : > FLASHE, PAGE = 0 .cinit : > FLASHC, PAGE = 0 .pinit : > FLASHC, PAGE = 0 .switch : > FLASHC, PAGE = 0 .econst : > FLASHB, PAGE = 1 //FFT Table FPUfftTables : LOAD = FLASHB, RUN = RAMLS012345, RUN_START(_FFTTwiddlesRunStart), LOAD_START(_FFTTwiddlesLoadStart), LOAD_SIZE(_FFTTwiddlesLoadSize), PAGE = 1, { --library=c28x_fpu_dsp_library_coff.lib (FPUfftTables) } FPUmathTables : LOAD = FLASHB, RUN = RAMLS012345, RUN_START(_FPUmathTablesRunStart), LOAD_START(_FPUmathTablesLoadStart), LOAD_SIZE(_FPUmathTablesLoadSize), PAGE = 1 #else #error Add either "RAM" or "FLASH" to C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define #endif //RAM ramgs515 : > RAMGS515, PAGE = 1 //FFT CFFT_In_data : > RAMGS515, PAGE = 1, ALIGN = CFFT_ALIGNMENT CFFT_Out_data : > RAMGS515, PAGE = 1 CFFT_Window_data : > RAMGS515, PAGE = 1 CFFT_Window_Org_data : > RAMGS515, PAGE = 1 Back_Ground_CFFT_data : > RAMGS515, PAGE = 1 Long_Range_CFFT_data : > RAMGS515, PAGE = 1 Long_Range_CFFT_Abs_data : > RAMGS515, PAGE = 1 Long_Range_CFFT_Abs_Ave_data : > RAMGS515, PAGE = 1 Short_Range_CFFT_Mag_data : > RAMGS515, PAGE = 1 Short_Range_CFFT_Phase_data : > RAMGS515, PAGE = 1 D_CFFT_In_data : > RAMGS515, PAGE = 1, ALIGN = CFFT_ALIGNMENT D_CFFT_In_Temp_data : > RAMGS515, PAGE = 1, ALIGN = CFFT_ALIGNMENT D_CFFT_Out_data : > RAMGS515, PAGE = 1 D_CFFT_Abs_Out_data : > RAMGS515, PAGE = 1 D_CFFT_Window_Org_data : > RAMGS515, PAGE = 1 Usb_TxBuffer : > RAMGS515, PAGE = 1 //TEST Data CFFT_Test_data : > RAMGS515, PAGE = 1, ALIGN = CFFT_ALIGNMENT .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ .cio : > RAMD01, PAGE = 1 .sysmem : > RAMD01, PAGE = 1 .stack : > RAMM1, PAGE = 1 .ebss : > RAMD01, PAGE = 1 .esysmem : > RAMD01, PAGE = 1 } /* //=========================================================================== // End of file. //=========================================================================== */