/*
  CAN Tx and Rx massage main.c */


#include "DSP28x_Project.h"

void main(void)
 {

	struct ECAN_REGS ECanaShadow;
	struct ECAN_REGS ECanbShadow;
	
	Uint16 temp;

InitSysCtrl();


DINT;

InitPieCtrl();

	// Disable CPU interrupts and clear all CPU interrupt flags:
	   IER = 0x0000;
	   IFR = 0x0000;

	   InitPieVectTable();

            EALLOW;


		    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;// Configure GPIO31 for CANTXA operation
                    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;// Configure GPIO30 for CANRXA operation

                    GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2;// Configure GPIO8 for CANTXB operation
                    GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2;  // Configure GPIO10 for CANRXB operation


				GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0;
				GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;
				GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;

	   EDIS;


InitECan();



ECanaMboxes.MBOX5.MSGID.all     = 0x95555555;
ECanaMboxes.MBOX5.MSGID.bit.IDE = 1;

ECanbMboxes.MBOX1.MSGID.all     = 0x95555555;
ECanbMboxes.MBOX1.MSGID.bit.IDE = 1;

/* Configure Mailbox 5 as transmit mailbox */

	ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
	ECanaShadow.CANMD.bit.MD5 = 0;
	ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

	/* Enable Mailbox 5  */
	ECanaShadow.CANME.all = ECanaRegs.CANME.all;
	ECanaShadow.CANME.bit.ME5 = 1;
	ECanaRegs.CANME.all = ECanaShadow.CANME.all;

	/* Write to DLC field in Master Control reg */
	ECanaMboxes.MBOX5.MSGCTRL.all = 0;
	ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;

	ECanaMboxes.MBOX5.MDL.all = 0x55555555;
	ECanaMboxes.MBOX5.MDH.all = 0x55555555;


/* Configure Mailbox 1 as Receive mailbox */

		ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;
		ECanbShadow.CANMD.bit.MD1 = 1;
		ECanbRegs.CANMD.all = ECanbShadow.CANMD.all;

		/* Enable Mailbox 1  */
		ECanbShadow.CANME.all = ECanbRegs.CANME.all;
		ECanbShadow.CANME.bit.ME1 = 1;
		ECanbRegs.CANME.all = ECanbShadow.CANME.all;

		/* Write to DLC field in Master Control reg */
		ECanbMboxes.MBOX1.MSGCTRL.all = 0;
		ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8;

	while(1)
	{

				ECanaShadow.CANTRS.all = 0;
			    ECanaShadow.CANTRS.bit.TRS5 = 1;     // Set TRS for mailbox under test
			    ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

			    do
			        	{
			    	ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
			        	}		    while(ECanaShadow.CANTA.bit.TA5 == 0 );// Wait for TA5 bit to be set.



			    	     	ECanaShadow.CANTA.all = 0;
			    	     	ECanaShadow.CANTA.bit.TA5 = 1;     	 // Clear Transmit Acknowledge #5
			    	     	ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;






	  	  if (ECanbRegs.CANRMP.bit.RMP1 == 1) ;// valid new data in MBX1?



	  	  			 	temp = ECanbMboxes.MBOX1.MDL.byte.BYTE0;	// read message
	  	  				ECanbRegs.CANRMP.bit.RMP1 = 1;			// clear the status flag RMP1

	  	  			if(temp & 1) 								// update LED LD1
	  	  								GpioDataRegs.GPBSET.bit.GPIO34 = 1;
	  	  							else
	  	  								GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1;


	  	  			// and prepare MBX1 for next receive






	  	  				}
 }