// TI File $Revision: /main/2 $
// Checkin $Date: July 30, 2009   18:44:22 $
//###########################################################################
// Filename: Example_28xEcan_A_to_B_Xmit.c
//
// Description: eCANA-1 to eCANA2 Transmit loop
//
// ASSUMPTIONS:
//
//    This program requires the DSP2833x header files.
//
//    The CAN ports A of the two 2833x DSP need to be connected
//    to each other (via CAN transceivers)0



//
//      Transmitter end- eCANA1 is on GPIO19 (CANTXA)  and
//                   GPIO18 (CANRXA)
//
//    Reciever end-  eCANA2 is on GPIO19  (CANTXB)  and
//                   GPIO18 (CANRXB)
//
//    As supplied, this project is configured for "boot to SARAM"
//    operation.  The 2833x Boot Mode table is shown below.
//    For information on configuring the boot mode of an eZdsp,
//    please refer to the documentation included with the eZdsp,
//
//       $Boot_Table:
//
//         GPIO87   GPIO86     GPIO85   GPIO84
//          XA15     XA14       XA13     XA12
//           PU       PU         PU       PU
//        ==========================================
//            1        1          1        1    Jump to Flash
//            1        1          1        0    SCI-A boot
//            1        1          0        1    SPI-A boot
//            1        1          0        0    I2C-A boot
//            1        0          1        1    eCAN-A boot
//            1        0          1        0    McBSP-A boot
//            1        0          0        1    Jump to XINTF x16
//            1        0          0        0    Jump to XINTF x32
//            0        1          1        1    Jump to OTP
//            0        1          1        0    Parallel GPIO I/O boot
//            0        1          0        1    Parallel XINTF boot
//            0        1          0        0    Jump to SARAM       <- "boot to SARAM"
//            0        0          1        1    Branch to check boot mode
//            0        0          1        0    Boot to flash, bypass ADC cal
//            0        0          0        1    Boot to SARAM, bypass ADC cal
//            0        0          0        0    Boot to SCI-A, bypass ADC cal
//                                              Boot_Table_End$
//
// DESCRIPTION:
//
//    This example TRANSMITS data from MAILBOX5, CANA on DSP1 to another DS2P CANA module MAILBOX1
//    This program could either loop forever or transmit "n" # of times,
//    where "n" is the TXCOUNT value.
//
// ###########################################################################

#include "DSP28x_Project.h"

// Prototype statements for functions found within this file.

// Global Variables

/* Create a shadow register structure for the CAN control registers. This is
 needed, since, only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents. This is
 especially true while writing to a bit (or group of bits) among bits 16 - 31 */

struct  ECAN_REGS ECanaShadow;

main()
{
// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
// This function is found in the DSP28_SysCtrl.c file.
    InitSysCtrl();

// Initialise the physical pins of the DSP
    //* Initialize the CAN module */

    InitECan();

/* Write to the MSGID field - MBX number is written as its MSGID */
    ECanaMboxes.MBOX2.MSGID.all  = 0x00050000;  // extended identifier
    ECanaMboxes.MBOX2.MSGID.bit.IDE = 0;

/* Configure Mailbox 1 as Receiver mailbox */
    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
    ECanaShadow.CANMD.bit.MD2 = 1;
    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
    ECanaMboxes.MBOX2.MSGCTRL.all  = 0;

    ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
/* Enable Mailbox 1  */

    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
    ECanaShadow.CANME.bit.ME2 = 1;
    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Begin Receiving */
   while(1)
    {
     do {
        ECanaShadow.CANRMP.all = ECanaRegs.CANRMP.all;
        }
        while(ECanaShadow.CANRMP.bit.RMP1 != 1 );       // Wait for RMP1 to be set..

     ECanaShadow.CANRMP.bit.RMP1 = 1;
     ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;    // Clear RMP1 bit and start again



    }

}