static void initSpiASlave(void)
{
    U16 regValue;

    // Must put SPI into reset before configuring it (disable SPI A module)
    //
    spiAREG1->SPI_O_CCR &= ~(SPI_CCR_SPISWRESET);

    //
    // Set polarity and data width.
    //
    regValue = 0U   << 6U  // CLKPOLARITY = 0U -> Data is output on rising edge and input on falling edge.
            |  0U   << 5U  // HS_MODE = disabled
            |  0xFU;       // SPICHAR = 16-bit word


    spiAREG1->SPI_O_CCR = (spiAREG1->SPI_O_CCR & 0xFF90) | regValue;

    //
    // Set the mode and phase.
    //
    regValue = 0U   << 4U  // OVERRUNINTENA = disabled
            |  0U   << 3U  // CLK_PHASE = Normal SPI clocking scheme
            |  0U   << 2U  // MASTER_SLAVE = Slave
            |  1U   << 1U  // TALK = enabled (slave sends data to master)
            |  0U;         // SPIINTENA = interrupt is enabled

    spiAREG1->SPI_O_CTL = (spiAREG1->SPI_O_CTL & 0xFFE0) | regValue;

    //
    // Enable the FIFO.
    //
    regValue = 0U  << 15U  // 0h (R/W) = Write 0 to reset the SPI transmit and receive channels
            |  0U  << 14U  // SPIFFENA = enhancements disabled
            |  1U  << 13U  // TXFIFO = Release transmit FIFO from reset
            |  0U  << 5U;  // TXFFIENA = FIFO interrupt disabled

    spiAREG1->SPI_O_FFTX = (spiAREG1->SPI_O_FFTX & 0x1FDF) | regValue;

    regValue = 1U  << 14U  // RXFFOVFCLR = clear SPIFFRX[RXFFOVF]
            |  1U  << 13U  // RXFIFORESET = Re-enable receive FIFO operation
            |  0U  << 5U;  // RXFFIENA = receive FIFO interrupt disabled

    spiAREG1->SPI_O_FFRX = (spiAREG1->SPI_O_FFRX & 0x9FDF) | regValue;

    spiAREG1->SPI_O_FFTX |= 1U  << 15U;  // 1h (R/W) = SPI FIFO can resume transmit or receive.

    //
    // Configuration complete. Enable the module.
    //
    spiAREG1->SPI_O_CCR |= SPI_CCR_SPISWRESET;
}