uint16_t 
IPCBootCPU2(uint32_t ulBootMode)
{
	uint32_t bootStatus;
    uint16_t pin;
    uint16_t returnStatus = STATUS_PASS;
    
	// If CPU2 has already booted, return a fail to let the application 
    // know that something is out of the ordinary.

    bootStatus = IPCGetBootStatus() & 0x0000000F;

	if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK)
    {
        returnStatus = STATUS_FAIL;
		
		return returnStatus;
    }

    // Wait until CPU02 control system boot ROM is ready to receive 
    // CPU01 to CPU02 INT1 interrupts. 
    do
    {
        bootStatus = IPCGetBootStatus() & 0x0000000F;    
    } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY));
             

    
    // Loop until CPU02 control system IPC flags 1 and 32 are available
    while ((IPCLtoRFlagBusy(IPC_FLAG0) == 1) || 
           (IPCLtoRFlagBusy(IPC_FLAG31) == 1))
    {

    }

    if (ulBootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE)
    {
        returnStatus = STATUS_FAIL;
    }
    else
    {
        // Based on boot mode, enable pull-ups on peripheral pins and 
        // give GPIO pin control to CPU02 control system.
        switch (ulBootMode)
        {
            case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI:

                 EALLOW;
                 //SCIA connected to CPU02
                 DevCfgRegs.CPUSEL5.bit.SCI_A = 1;	
                 //Allows CPU02 bootrom to take control of clock 
                 //configuration registers
                 ClkCfgRegs.CLKSEM.all = 0xA5A50000;	

                 ClkCfgRegs.LOSPCP.all = 0x0002;
                 EDIS;
                 
                 GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(29,GPIO_MUX_CPU2,1);
                 
                 GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(28,GPIO_MUX_CPU2,1);
                 
                break;

            case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI:
                 EALLOW;
                 //SPI-A connected to CPU02
                 DevCfgRegs.CPUSEL6.bit.SPI_A = 1;	
                 //Allows CPU02 bootrom to take control of clock configuration registers
                 ClkCfgRegs.CLKSEM.all = 0xA5A50000;
                 EDIS;
                 
                 GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(16,GPIO_MUX_CPU2,1);
                 
                 GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(17,GPIO_MUX_CPU2,1);
                 
                 GPIO_SetupPinOptions(18, GPIO_INPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(18,GPIO_MUX_CPU2,1);
                 
                 GPIO_SetupPinOptions(19, GPIO_OUTPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(19,GPIO_MUX_CPU2,0);          
                 
                break;
                
            case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C:
                 EALLOW;
                 //I2CA connected to CPU02
                 DevCfgRegs.CPUSEL7.bit.I2C_A = 1;	
                 //Allows CPU2 bootrom to take control of clock 
                 //configuration registers
                 ClkCfgRegs.CLKSEM.all = 0xA5A50000;	
                 ClkCfgRegs.LOSPCP.all = 0x0002;
                 EDIS;
                 GPIO_SetupPinOptions(32, GPIO_INPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(32,GPIO_MUX_CPU2,1);
                 
                 GPIO_SetupPinOptions(33, GPIO_INPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(33,GPIO_MUX_CPU2,1);
                 
                break;
            case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL:
                 
                 
                 for(pin=58;pin<=65;pin++)
                 {
                    GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC);
                    GPIO_SetupPinMux(pin,GPIO_MUX_CPU2,0);
                 }
                 
                 GPIO_SetupPinOptions(69, GPIO_OUTPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(69,GPIO_MUX_CPU2,0);
                 
                 GPIO_SetupPinOptions(70, GPIO_INPUT, GPIO_ASYNC);
                 GPIO_SetupPinMux(70,GPIO_MUX_CPU2,0);             
                 break;
               
               
            case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN:
                 //Set up the GPIO mux to bring out CANATX on GPIO71 
                 //and CANARX on GPIO70
                 EALLOW;
                 GpioCtrlRegs.GPCLOCK.all = 0x00000000;	//Unlock GPIOs 64-95
                 GpioCtrlRegs.GPCCSEL1.bit.GPIO71 = GPIO_MUX_CPU2;	//Give CPU2 control just in case
                 GpioCtrlRegs.GPCGMUX1.bit.GPIO71 = 0x1;	//Set the extended mux to 0x5
                 GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 0x1;
                 GpioCtrlRegs.GPCQSEL1.bit.GPIO71 = 0x3;	//Set qualification to async just in case
                 
                 GpioCtrlRegs.GPCLOCK.all = 0x00000000;	//Unlock GPIOs 64-95
                 GpioCtrlRegs.GPCCSEL1.bit.GPIO70 = GPIO_MUX_CPU2;	//Give CPU2 control just in case
                 GpioCtrlRegs.GPCGMUX1.bit.GPIO70 = 0x1;	//Set the extended mux to bring out CANATX
                 GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 0x1;
                 GpioCtrlRegs.GPCQSEL1.bit.GPIO70 = 0x3;	//Set qualification to async just in case
                 GpioCtrlRegs.GPCLOCK.all = 0xFFFFFFFF;	//Lock GPIOs 64-95
                 ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = 0x0;
                 CpuSysRegs.PCLKCR10.bit.CAN_A = 1;
                 EDIS;   
               
               break;
               
         }
       
        //CPU01 to CPU02 IPC Boot Mode Register
        IpcRegs.IPCBOOTMODE = ulBootMode;
        // CPU01 To CPU02 IPC Command Register
        IpcRegs.IPCSENDCOM  = BROM_IPC_EXECUTE_BOOTMODE_CMD;
        // CPU01 to CPU02 IPC flag register
        IpcRegs.IPCSET.all = 0x80000001;
               
    }
  


    return returnStatus;
}