//############################################################################# // // FILE: f28p65x_cla_c_lnk.cmd // // TITLE: Linker Command File for CLA Math library examples that run // on the f28003x platform // // This file includes all RAM and FLASH blocks present on the // f28003x and depending on the active build configuration // (RAM or FLASH) the appropriate sections will either be loaded // into RAM or FLASH blocks // //########################################################################### // // // $Copyright: Copyright (C) 2023 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### // // CLA_C is defined to 1 in the project properties // Project Properties -> C2000 Linker -> Advanced Options -> Command File // Preprocessing -> --define // //--define=CLA_C=1 // // CLA_MATH_TABLES_IN_ROM is defined in the project properties according to // build configuration selected // Project Properties -> C2000 Linker -> Advanced Options -> Command File // Preprocessing -> --define --define=CLA_MATH_TABLES_IN_ROM=1 // Set this variable to 1 to use the CLA Math Tables in the CLA Data ROM // If set to 0, make sure the right CLA Math library (one without the _datarom // suffix) is used in the project // // #include "..\..\..\..\..\Sources\Devices\OBC\Common\Abstraction\F28P65\sys_mem_map.h" CLAsincosTable = 0xFD0A; CLAsincosTable_TABLE_SIZEDivTwoPi = 0xFE4E; CLAsincosTable_TwoPiDivTABLE_SIZE = 0xFE50; CLAsincosTable_TABLE_MASK = 0xFE52; CLAsincosTable_Coef0 = 0xFE54; CLAsincosTable_Coef1 = 0xFE56; CLAsincosTable_Coef1_pos = 0xFE58; CLAsincosTable_Coef2 = 0xFE5A; CLAsincosTable_Coef3 = 0xFE5C; CLAsincosTable_Coef3_neg = 0xFE5E; MEMORY { BEGIN_M0 : origin = 0x000000, length = 0x000002 /* Part of M0 RAM - used for "Boot to M0" bootloader mode */ BOOT_RSVD : origin = 0x000002, length = 0x0001C0 /* Part of M0 RAM, BOOT rom will use this for stack see doc. TMS320F28P65x Microcontrollers - Technical reference manual at par. 3.7.6.2 Reserved RAM Memory maps */ RAMM0 : origin = RAMM0_START, length = RAMM0_LENGTH /* M0 RAM */ BOOT_BOOT_RAM (RW) : origin = BOOT_BOOT_RAM_START, length = BOOT_BOOT_RAM_LENGTH /* Variables stored in uninitialzed RAM: R/W from bootloader, not readable/writable from application */ APPL_BOOT_RAM (RW) : origin = BOOT_APPL_RAM_START, length = BOOT_APPL_RAM_LENGTH /* Variables stored in uninitialzed RAM: R/W from both bootloader and application */ APPL_APPL_RAM (RW) : origin = APPL_APPL_RAM_START, length = APPL_APPL_RAM_LENGTH /* Variables stored in uninitialzed RAM: R/W from application, R from bootloader */ RAMM1 : origin = 0x000400, length = 0x000400 /* M1 RAM */ // RAMLS0 : origin = 0x008000, length = 0x000800 /* LS0 RAM, DCSM secure */ RAM_CLADATA : origin = 0x008000, length = 0x000800 /* LS0 RAM, DCSM secure, CLA Data RAM */ // RAM_CLAPROG : origin = 0x008800, length = 0x002800 /* LS1 + LS2 + LS3 + LS4 + LS5 */ // RAMLS1 : origin = 0x008800, length = 0x000800 /* LS1 RAM, DCSM secure */ RAMLS1_STACK : origin = 0x008800, length = 0x000800 /* LS1 RAM, DCSM secure */ RAMLS2 : origin = 0x009000, length = 0x000800 /* LS2 RAM, DCSM secure */ RAMLS3 : origin = 0x009800, length = 0x000800 /* LS3 RAM, DCSM secure */ RAMLS4 : origin = 0x00A000, length = 0x000800 /* LS4 RAM, DCSM secure */ RAMLS5 : origin = 0x00A800, length = 0x000800 /* LS5 RAM, DCSM secure */ RAMLS6 : origin = 0x00B000, length = 0x000800 /* LS5 RAM, DCSM secure */ RAMLS7 : origin = 0x00B800, length = 0x000800 /* LS7 RAM, DCSM secure */ // RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000 // RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000 RAMLS8LS9CLALOAD : origin = 0x022000, length = 0x004000 // Reserved to copy in runtime the CLA code (see DATASHEET at par. C28x Memory Map) // LS8/LS9 have different addresses depending on the user (CPU or CLA) // CLA code is copied by CPU at address 0x22000 and is executed by CLA from address 0x4000 // RAM_LS8CLAPROG : origin = 0x004000, length = 0x002000 /* LS8, DCSM secure, CLA Program RAM, not accessible for CPU */ // RAM_LS9CLAPROG : origin = 0x006000, length = 0x002000 /* LS9, DCSM secure, CLA Program RAM, not accessible for CPU */ RAM_LS8LS9CLAPROG : origin = 0x004000, length = 0x004000 /* LS8+LS9, DCSM secure, CLA Program RAM, not accessible for CPU */ // this is the sector where the CLA runs its program, after it has been loaded in RAM by the CPU // (in sector RAMLS8LS9CLALOAD) RAMD0 : origin = 0x00C000, length = 0x002000 RAMD1 : origin = 0x00E000, length = 0x002000 RAMD2 : origin = 0x01A000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection RAMD3 : origin = 0x01C000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection RAMD4 : origin = 0x01E000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection RAMD5 : origin = 0x020000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection // CLA1_DATAROM : origin = 0x00F000, length = 0x001000 RAMGS0_FLASHFUNC : origin = 0x010000, length = 0x001400 /* GS0-1 RAM, Parity, DMA */ RAMGS0 : origin = 0x011400, length = 0x000C00 /* GS0-2 RAM, Parity, DMA */ RAMGS1 : origin = 0x012000, length = 0x002000 /* GS1 RAM, Parity, DMA */ RAMGS2 : origin = 0x014000, length = 0x002000 /* GS2 RAM, Parity, DMA */ RAMGS3 : origin = 0x016000, length = 0x002000 /* GS3 RAM, Parity, DMA */ RAMGS4 : origin = 0x018000, length = 0x002000 /* GS4 RAM, Parity, DMA */ /* Flash sectors */ /* BANK 0 */ BOOT_SW_VERSION : origin = BOOT_SW_VER_START , length = BOOT_SW_VER_LENGTH BOOT_SWIDDATAID : origin = BOOT_SWIDDATAID_START , length = BOOT_SWIDDATAID_LENGTH BOOT_TEXT : origin = BOOT_START_CODE , length = BOOT_LENGTH_CODE HARDWARE_VERSION : origin = HW_VERSION_START , length = HW_VERSION_LENGTH HARDWARE_VARIANT : origin = HW_VARIANT_START , length = HW_VARIANT_LENGTH CALIB_SECTION : origin = CALIB_START , length = CALIB_LENGTH BEGIN_FLASH : origin = APPL_CODESTART_START , length = APPL_CODESTART_LENGTH /* Part of FLASH_BANK1_SEC0 - used for "Jump to flash" bootloader mode (in application program) */ APPL_SW_VERSION : origin = APPL_SWVER_START , length = APPL_SWVER_LENGTH APPL_SWIDDATAID : origin = APPL_SWIDDATAID_START , length = APPL_SWIDDATAID_LENGTH APPL_TEXT_B0 : origin = APPL_BANK0_CODESTART , length = APPL_BANK0_LENGTH /* , FILL = 0xFFFF */ /* FILL is not more needed because the CRC is computed offline by a python script and introduced into the S3 file */ A_FLASH_BANK0_CLA : origin = APPL_CLA_FLASH_START , length = APPL_CLA_FLASH_LENGTH A_HARDWARE_VERSION : origin = APPL_HW_VERSION_START , length = HW_VERSION_LENGTH A_HARDWARE_VARIANT : origin = APPL_HW_VARIANT_START , length = HW_VARIANT_LENGTH APPL_CRC_TAB_RES : origin = APPLICATION_CRC_START , length = APPLICATION_CRC_LENGTH /* Flash sectors */ /* BANK 1 */ APPL_TEXT_B1 : origin = APPL_BANK1_CODESTART , length = APPL_BANK1_LENGTH /* , FILL = 0xFFFF*/ /* The FILL to 0xFFFF is used in order to emulate the erased blank flash sector. This will allow the CRC computation to be coherent between the linker and the bootloader software check at run-time. WARNING: if no FILL directive is used, the HOLES will be automatically filled with 0x0000! This behaviour is wrong since, after a full memory erase, the erased cells value is 0xFFFF FILL is not more needed because the CRC is computed offline by a python script and introduced into the S3 file */ /* Flash sectors */ /* BANK 2 */ APPL_TEXT_B2 : origin = APPL_BANK2_CODESTART , length = APPL_BANK2_LENGTH /* , FILL = 0xFFFF*/ /* The FILL to 0xFFFF is used in order to emulate the erased blank flash sector. This will allow the CRC computation to be coherent between the linker and the bootloader software check at run-time. WARNING: if no FILL directive is used, the HOLES will be automatically filled with 0x0000! This behaviour is wrong since, after a full memory erase, the erased cells value is 0xFFFF FILL is not more needed because the CRC is computed offline by a python script and introduced into the S3 file */ CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800 CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800 CLATOCPURAM : origin = 0x001480, length = 0x000080 CPUTOCLARAM : origin = 0x001500, length = 0x000080 CLATODMARAM : origin = 0x001680, length = 0x000080 DMATOCLARAM : origin = 0x001700, length = 0x000080 CANA_MSG_RAM : origin = 0x049000, length = 0x000800 CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 RESET (R) : origin = 0x3FFFC0, length = 0x000002 /* Part of Boot ROM */ } SECTIONS { /*** Compiler Required Sections ***/ /* Flash memory (PAGE 0) sections */ /* * this section is only a placeholder to be used in case of need to check tha CRC algorythm usign a known pattern * otherwise it is not necessary because the CRC is computed and inserted in the SRec by an offline script * following the TI CRC structure explained below */ /* .dummy_checked_section: > APPL_TEXT_B0 | APPL_TEXT_B1, PAGE = 0, crc_table(_crcTableAppl) */ .text : >> APPL_TEXT_B0 | APPL_TEXT_B1 | APPL_TEXT_B2, ALIGN(4) /* , crc_table(_crcTableAppl) */ .cinit : > APPL_TEXT_B1, ALIGN(4) #if defined(__TI_EABI__) .const : > APPL_TEXT_B0, ALIGN(4) #else .econst : > APPL_TEXT_B0, ALIGN(4) #endif #if defined(__TI_EABI__) .init_array : > APPL_TEXT_B0, ALIGN(4) #else .pinit : > APPL_TEXT_B0, ALIGN(4) #endif .switch : > APPL_TEXT_B0, ALIGN(4) /* This generates a custom Output Section that contains all the input sections listed below. This is used to compute a single record for the crc_table, which is going to be stored in the section named .TI.crctab */ /* Pay attention: this method computes the CRC only over the sections indicated below (NOT ON THE OVERALL FLASH) It seems not to be very flexible to compute the CRC over the complete Flash This could become a stakeholder ---> the CRC should be computed with an external tool over the complete Flash area used by the application (BANK0 + BANK1) and written offline at the address APPLICATION_CRC_START usign the structure described in TI document Sector APPL_CRC_TAB_RES can contain up to 10 CRC with the following structure typedef struct crc_table { uint16_t rec_size; --> usually 8 uint16_t num_recs; --> indicates the number of following valid records (min 1) CRC_RECORD recs[num_recs]; } CRC_TABLE; each record has the following structure typedef struct crc_record { uint16_t crc_alg_ID; --> CRC algorithm ID --> depends on teh algo used (usually 0 = CRC32_PRIME) uint16_t page_id; --> usually 0 uint32_t addr; --> Starting address uint32_t size; --> size of data in 16-bit units uint32_t crc_value; } CRC_RECORD; */ /* .crctableappl { *(.text) *(.cinit) *(.const) *(.econst) *(.pinit) *(.switch) } > APPL_TEXT_B0 | APPL_TEXT_B1, crc_table(_crcTableAppl) */ /* to be used only in case of test/debug .DummyCalibFEE1 : > CALIB_SECTION1, PAGE = 0 .DummyCalibFEE2 : > CALIB_SECTION2, PAGE = 0 */ .reset : > RESET, TYPE = DSECT .TI.crctab : > APPL_CRC_TAB_RES /* section where the linker place the Appl CRC -> currently used only if section .dummy_checked_section is defined But usually not necessary because the CRC is computed offline */ .applswversion : > APPL_SW_VERSION Applcodestart : > BEGIN_FLASH, ALIGN(4) /* Used by file CodeStartBranch.asm */ .bootswversion : > BOOT_SW_VERSION .HwVersion : > HARDWARE_VERSION .HwVariant : > HARDWARE_VARIANT .A_HwVersion : > A_HARDWARE_VERSION .A_HwVariant : > A_HARDWARE_VARIANT .applswversiondataid : > APPL_SWIDDATAID .bootswversiondataid : > BOOT_SWIDDATAID .crctableappl : > APPL_CRC_TAB_RES /* This section is linked to the same sector as the CRC because is not really used Used only to prevent a linker warning when the application tries to allocate the section .crcTableAppl that contains a dummy variable crcTableAppl This variable is not allocated in the Application because not used */ MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT GROUP { .TI.ramfunc { -l FAPI_F28P65x_EABI_v3.00.00.lib } /** forces Flash API to be loaded in RAM **/ } LOAD = APPL_TEXT_B1, RUN = RAMGS0_FLASHFUNC #if defined(__TI_EABI__) LOAD_START(RamfuncsLoadStart), LOAD_SIZE(RamfuncsLoadSize), LOAD_END(RamfuncsLoadEnd), RUN_START(RamfuncsRunStart), RUN_SIZE(RamfuncsRunSize), RUN_END(RamfuncsRunEnd), #else LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), #endif ALIGN(4) /************************************************* * DEFINITION OF CLA SPECIFIC SECTIONS ************************************************/ /* #if defined(CLA_USED) */ #if defined(__TI_EABI__) /** Cla1Prog is the output section where the compiler allocates by default the CLA code -- this a symbol necessary **/ Cla1Prog : LOAD = A_FLASH_BANK0_CLA, RUN = RAM_LS8LS9CLAPROG, LOAD_START(Cla1ProgFlashLoadStart), /* RUN_START(Cla1ProgRunStart), */ /** this symbol is not necessary in this implementation, because the cose is loaded NOT at the same address as RUN **/ LOAD_SIZE(Cla1ProgLoadSize), ALIGN(4) /* * ClaCodeRamLoad is the output section customized for 28P65 in order to generate the symbol "ClaCodeRamLoadStart" * that is used to LOAD the code at a specific RAM memory sector that is not the same used to RUN the CLA code * see DATASHEET at par. C28x Memory Map */ ClaCodeRamLoad : LOAD = RAMLS8LS9CLALOAD, LOAD_START(ClaProgRamLoadStart), ALIGN(4) #else /* defined(__TI_EABI__) */ /* CLA specific sections */ Cla1Prog : LOAD = A_FLASH_BANK0_CLA, RUN = RAM_LS8LS9CLAPROG, LOAD_START(_Cla1ProgFlashLoadStart), /* RUN_START(_Cla1ProgRunStart), */ LOAD_SIZE(_Cla1ProgLoadSize), ALIGN(4) ClaCodeRamLoad : LOAD = RAMLS8LS9CLALOAD, LOAD_START(_ClaProgRamLoadStart), ALIGN(4) #endif Cla1ToCpuMsgRAM : > CLATOCPURAM CpuToCla1MsgRAM : > CPUTOCLARAM Cla1DataRam : > RAM_CLADATA .scratchpad : > RAM_CLADATA .bss_cla : > RAM_CLADATA cla_shared : > RAM_CLADATA #if defined(__TI_EABI__) .const_cla : LOAD = A_FLASH_BANK0_CLA, RUN = RAM_CLADATA, RUN_START(Cla1ConstRunStart), LOAD_START(Cla1ConstLoadStart), LOAD_SIZE(Cla1ConstLoadSize), ALIGN(4) #if !defined (CLA_MATH_TABLES_IN_ROM) CLA1mathTables : LOAD = A_FLASH_BANK0_CLA, RUN = RAM_CLADATA, RUN_START(CLA1mathTablesRunStart), LOAD_START(CLA1mathTablesLoadStart), LOAD_SIZE(CLA1mathTablesLoadSize), ALIGN(4) #endif #else .const_cla : LOAD = A_FLASH_BANK0_CLA, RUN = RAM_CLADATA, RUN_START(_Cla1ConstRunStart), LOAD_START(_Cla1ConstLoadStart), LOAD_SIZE(_Cla1ConstLoadSize), ALIGN(4) #if !defined (CLA_MATH_TABLES_IN_ROM) CLA1mathTables : LOAD = A_FLASH_BANK0_CLA, RUN = RAM_CLADATA, RUN_START(_CLA1mathTablesRunStart), LOAD_START(_CLA1mathTablesLoadStart), LOAD_SIZE(_CLA1mathTablesLoadSize), ALIGN(4) #endif #endif /* #endif */ /* defined(CLA_USED) */ /************************************************* * DEFINITION OF CLA SPECIFIC SECTIONS ************************************************/ #if defined(__TI_EABI__) .bss : >> RAMGS0 | RAMGS1 .data : >> RAMM0 | RAMM1 /* only EABI format */ #else .ebss : > RAMLS01 #endif /* .cio : > RAMM0, PAGE = 1 */ .stack : > RAMLS1_STACK /* RAMM1 */ #if defined(__TI_EABI__) .sysmem : > RAMM1 #else .esysmem : > RAMM1 #endif /* in EABI format, set type NOINIT to ask explicitely to not initialize those sections */ #if defined(__TI_EABI__) .bootbootshared : > BOOT_BOOT_RAM, type = NOINIT type = DSECT .bootapplshared : > APPL_BOOT_RAM, type = NOINIT .applapplshared : > APPL_APPL_RAM, type = NOINIT #else .bootbootshared : > BOOT_BOOT_RAM, type = DSECT .bootapplshared : > APPL_BOOT_RAM .applapplshared : > APPL_APPL_RAM #endif } /* //=========================================================================== // End of file. //=========================================================================== */