AFE80xxCatLibrary
spi - USB Instrument created.
resetDevice
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
FPGA reset - USB Instrument created.
Power Card - USB Instrument created.
Version : 0x101204c
Connected to Capture Card
Loaded Libraries
Loaded Configuration: AFE8000_SampleConfig.xlsx
Refreshed the GUI.
#================ ERRORS:0, WARNINGS:0 ================#
Loaded Configuration: AFE8000_SampleConfig.xlsx
Refreshed the GUI.
Device Initialization for ChipVersion: 2.0
The External Sysref Frequency should be an integer factor of: 3.90625MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 24750.0
laneRateRx1: 24750.0
laneRateFb: 24750.0
laneRateTx0: 24750.0
laneRateTx1: 24750.0
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 24750.0
laneRateRx1: 24750.0
laneRateFb: 24750.0
laneRateTx0: 24750.0
laneRateTx1: 24750.0
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
LMK and FPGA Configured.
DONOT_OPEN_Afe80xx_FULL - Device registers reset.
chipType: 0xa
chipId: 0x8001
chipVersion: 0x20
Programing FPGA ....
Resetting FPGA Pin.
Version : 0x101204c
Connected to Capture Card
Resetting FPGA.
Version : 0x101204c
Connected to Capture Card
LMK and FPGA Configured.
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
//Firmware Version = 9108
//PG Version = 1
//Release Date [dd/mm/yy] = 28/8/20
//Patch Version = 0
//PG Version = 0
//Release Date [dd/mm/yy] = 0/0/0
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE PAP and Alarms configured.
AFE GPIO configured.
Sysref Read as expected
FPGA Tx sysref captured
FPGA Rx sysref captured
FPGA Tx sysref captured
FPGA Rx sysref captured
Setting RBD to: 11
Setting RBD to: 11
FPGA Tx sysref captured
FPGA Rx sysref captured
FPGA Tx sysref captured
FPGA Rx sysref captured
Setting RBD to: 11
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b00000000 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b00000000 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1
###################################
AFE Configuration Complete
#================ ERRORS:3, WARNINGS:0 ================#