;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
;                                                                             
;   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
;   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
;   product  is  protected  under  copyright  law  and  trade  secret law as an 
;   unpublished work.  Created 2010, (C) Copyright 1997 Texas Instruments.  All 
;   rights reserved.                                                            
;                  
;                                                           
;   Filename       	: pri.h
;
;   Description    	: pri coprocessor header file 

;
;   Version number	: 1
;
;   Date 		: 28/6/2010 
;
;
;*************************************************************************
; Operation code are assumed as follows


INT_LOCK_MSK        .equ     0x000000C0              ; Interrupt lockout mask value


INFO_SP     .equ   0        ; Used for Single Precision operation
INFO_DP     .equ   1        ; Used for Double Precision operation

NO_OP	    .equ   0        ; No operation
F_ADD       .equ   1        ; Addition 
F_SUB       .equ   2        ; Substraction
F_MUL       .equ   3        ; Multiplication
F_DIV       .equ   4        ; Division
F_DADD      .equ   1        ;Double precision Addition
F_DSUB      .equ   2        ;Double precision Substraction
F_DMUL      .equ   3        ;Double precision Mulitplication
F_DDIV      .equ   4        ;Double precision Division
F_CMP       .equ   5        ;Single precision Comparison
F_DCMP      .equ   5        ;Double precision Comparion


ResultReg0    .equ     C4
ResultReg1    .equ     C5 
SP_OP1        .equ     C0
SP_OP2        .equ     C1
DP_OP1        .equ     C0
DP_OP2        .equ     C2
CPSR_FLAG_MSK .equ     0x000000FF

CLEAR_UIDFLAG_MSK   .equ     0xF0000000 

      .state32

;*********************MACROS FOR Transfer of Operands From /To ARM/CO_OP***********************
MOVE_OP_SP .macro   ;Move the operands for Single precision operation to CO_OP registers
           MCRAL p5,#NO_OP,R0,C0,C0    ;Move R0->CP0
           MCRAL p5,#NO_OP,R1,C1,C1    ;Move R1->CP1
           .endm

MOVE_OP_DP .macro ; Move the operands for Double precision operation to CO_OP registers
            MCRAL p5,#NO_OP,R0,C1,C1    ;Move R0->CP1
            MCRAL p5,#NO_OP,R1,C0,C0    ;Move R1->CP0
            MCRAL p5,#NO_OP,R2,C3,C3    ;Move R2->CP3
            MCRAL p5,#NO_OP,R3,C2,C2    ;Move R3->CP2
            .endm

MOVE_RESTOARM_SP .macro ; transfer the Single precision operation result to ARM regsiter macro
                  MRCAL p5,#NO_OP,R0,ResultReg0,ResultReg0  ; Transfer the result , ARM register R0
                 .endm


MOVE_RESTOARM_DP .macro  ; transfer the Double precision operation result to ARM regsiter macro
                  MRCAL p5,#NO_OP,R0,ResultReg1,ResultReg1  ; Transfer the result , ARM register R0
                  MRCAL p5,#NO_OP,R1,ResultReg0,ResultReg0  ; Transfer the result , ARM register R1
                  .endm
;**************************************************************************************************
INT_LOCK  .macro    ; Lock the interupts during pri instruction execution
           STMFD    SP!,{R7-R8}                    ;Save the R8 onto Stack  
           MRS   R8,CPSR                        ;Save the CPSR in R8
           MOV   R7,R8
           ORR  R7, R7,#INT_LOCK_MSK
           MSR   CPSR,R7          ;Setup the new CPSR with FIQ and IRQ disable
          .endm 
	   
INT_UNLOCK    .macro
               MSR CPSR,R8
               LDMFD SP!,{R7-R8}
               .endm 
 
INT_LOCK_CMP  .macro    ; Lock the interupts during pri instruction execution
           STMFD    SP!,{R6,R7,R8}                        ;Save the CPSR onto stack
           MRS      R7,CPSR                        ;Save the CPSR in R8
           MOV      R8,R7
           ORR      R8, R8,#INT_LOCK_MSK
	   MSR      CPSR,R8          ;Setup the new CPSR with FIQ and IRQ disable
          .endm

CPSR_RESTORE_CMP   .macro                         ; For compare intruction the N,Z,C & V flag need to be taken care of
                   MRCAL p5,#NO_OP,R6,C8,C8       ;Transfer the C8 contents to register R6
	           AND   R6,R6,#CLEAR_UIDFLAG_MSK ;Clear the 27,26 and 25th bit if was set due to CDP operation
  	           AND   R7,R7,#CPSR_FLAG_MSK      ;Clear the N,Z,C and V flags bits  
		   ORR   R6,R6,R7                  ;Restore the CPSR regsiter contents excpet the N,Z,C and V flag 
	           MSR   CPSR,R6                       ;Setup the new CPSR
                    LDMFD SP!,{ R6,R7,R8}
	           .endm