!3wire mode
!System Clock PLL mode with NO SCLK input mode. Provide supply voltages(3.3V). Don't provide I2S clocks yet. 
! Write 0x00 at address=0x00 via I2C. (Go to page.0)
X00 00  
! Write 0x10 at address=0x02 via I2C. (Standby request) 
X02 10  
! Write 0x5A at address=0x25 via I2C. (Ignore SCLK hault detector, Ignore SCLK detection, disable auto divider settings, ignore fs detection) 
X25 5A  
! Write 0x10 at address=0x0D via I2C. (PLL clock source => BCLK)
X0D 10 
! Write 0x00 at address=0x14 via I2C. (P=1 for PLL divider) 
X14 00
! Write (0x10 for BCLK=64fs, 0x20 for BCLK=32fs note that L&R 32 bit = 32*2=64) at address=0x15 via I2C. (J=16/32 for PLL divider) 
X15 10
! Write 0x00 at address=0x16 via I2C. (D1=0 for PLL divider)
X16 00   
! Write 0x00 at address=0x17 via I2C. (D2=0 for PLL divider)
X17 00   
! Write 0x01 at address=0x18 via I2C. (R=2 for PLL divider)
X18 01   
! Write 0x01 at address=0x1B via I2C. (miniDSP CLK divider = 2)
X1B 01   
! Write 0x0F at address=0x1C via I2C. (DAC CLK divider = 16)
X1C 0F   
! Write 0x03 at address=0x1D via I2C. (NCP CLK divider = 4) 
X1D 03  
! Write 0x07 at address=0x1E via I2C. (OSR CLK divider = 8) 
X1E 07  
! Write 0x00 at address=0x22 via I2C. (Interpolation filter = 8x, fs setting = 48kHz) 
X22 00
! Write 0x04 at address=0x23 via I2C. (IDAC = 1024 cycles) 
X23 04
! Write 0x00 at address=0x24 via I2C. (IDAC = 1024 cycles) 
X24 00
! Write 0x00 at address=0x02 via I2C. (Standby release) 
X02 00  
! Provide I2S clocks (SCLK : Tie to 0, LRCLK : 44.1kHz/48kHz, BCLK : 32fs/64fs)