/* First Play */ 00 00 /* Select Page 0*/ 01 01 /* S/W Reset to initialize all registers*/ 00 00 /* Select Page 0*/ 1B 00 /* AudioInterface = I2S, DataWordlength = 16bits, BCLK is input to the device, WCLK is input to the device, DOUT will not be high impedance while Audio Interface is active.*/ 00 00 /* Select Page 0*/ 04 07 /* Low PLL Clock Range, BCLK is input to PLL, PLL Clock is CODEC_CLKIN*/ 06 14 /* PLL J Values: J = 20 */ 07 00 /* PLL D Values: D = 0 */ 08 00 05 93 /* PLL is powered up, PLL P value: P = 1, PLL R value: R = 3 */ 0B 85 /* NDAC divider powered up, NDAC = 5 */ 0C 83 /* MDAC divider powered up, MDAC = 3 */ 0D 00 /* DOSR = 128 */ 0E 80 00 01 /* Select Page 1*/ 01 08 /* Disabled weak connection of AVDD with DVDD*/ 02 01 /* DVDD LDO output is nominally 1.72V, AVDD LDO output is nominally 1.72V, Analog Blocks Disabled, Over Current not detected for DVDD LDO & AVDD LDO, AVDD LDO Powered up*/ 47 32 /* Analog inputs power up time is 6.4ms*/ 7B 01 /* Reference will power up in 40ms when analog blocks are powered up*/ 00 00 /* Select Page 0*/ 3C 02) /* miniDSP_A & miniDSP_D are independently powered up, miniDSP_D is powered down with DAC Channel Power Down, DAC Signal Processing Block PRB_P2*/ 00 2C /* Select Page 44*/ 01 04 /* Adaptive Filtering enabled for DAC, DAC Coefficient Buffers will not be switched at next frame boundary*/ 00 01 /* Select Page 1*/ 0E 08 /* Left Channel DAC reconstruction filter output is routed to LOL, Right Channel DAC reconstruction filter's negative terminal & MAL output & LOR output are not routed to LOL*/ 0F 08 /* Right Channel DAC reconstruction filter output is routed to LOR, MAR output is not routed to LOR*/ 12 3A /* LOL driver is not muted, LOL driver gain is -6dB*/ 13 3A /* LOR driver is not muted, LOR driver gain is -6dB*/ 09 0C /* Power up LOL/LOR drivers, HPL/HPR/MAL/MAR are powered down*/ 00 00 /* Select Page 0*/ 3F D4 /* L/R DAC Channel Powered Up, Left DAC data Left Channel Audio Interface Data, Right DAC data Right Channel Audio Interface Data, Soft-Stepping is 1 step per 1 DAC Word Clock*/ 40 0C /* When Right DAC Channel is powered down, the data is zero, Auto Mute disabled, L/R DAC Channel muted, L/R Channel have independent volume control*/ 00 00 /* Select Page 0*/ 41 82 /* L/R Digital Volume Control = -63dB */ 42 82 00 00 /* Select Page 0*/ 40 00 /* L/R DAC Channel not muted*/ 41 00 /* L/R Digital Volume Control = 0dB */ 42 00