# BCLK = 1.536MHz; WCLK = 48kHz
# MCLK = 24.576MHz
#
# Page 0
w 30 00 00
#
# Software reset
w 30 01 80
#
# PLL Programming (Q = 4)
w 30 03 20
#
# Clock Register
w 30 65 01
#
# Master mode
w 30 08 c0
#
# Codec Data-Path Setup
w 30 07 8A
#
# DAC Power and Output Power Control
w 30 25 C0
#
# DAC Output Switching Control
w 30 29 02
#
# Left-DAC Digital Volume Control
w 30 2B 00
#
# DAC_L1 to LEFT_LOP/M
w 30 52 80
#
# DAC_R1 to RIGHT_LOP/M
w 30 5C 80
#
# LEFT_LOP/M Output Level
w 30 56 09
#
# RIGHT_LOP/M Output Level
w 30 5D 09