//MCLK = 11.2896MHz; BCLK = 2.8224MHz; WCLK = 44.1KHz

w 30 00 00			//Page 0
w 30 01 01			//Software reset
w 30 00 01			//Page 1
w 30 01 08			//Disabled weak connection of AVDD with DVDD
w 30 02 00			//Analog Blocks Enabled
w 30 47 32			//Analog inputs power up time
w 30 7B 01			//Reference will power up in 40ms when analog blocks are powered up
w 30 00 00			//Page 0
w 30 0D 00			//DAC OSR(MSB)
w 30 0E 80			//DAC OSR(LSB)
w 30 12 81			//NADC powered up; NADC=1
w 30 13 82			//MADC powered up; MADC=2
w 30 0B 81			//NDAC powered up; NDAC=1
w 30 0C 82			//MDAC powered up; MDAC=2
w 30 00 01			//Page 1
w 30 33 78			//MICBIAS configuration register		
w 30 34 04			//IN3L is routed to left MICPGA(P) with 10k res
w 30 36 04			//IN3R is routed to right MICPGA(M) with 10k res
w 30 3B 00 00			//Left MICPGA is enabled
w 30 00 00			//Page 0
w 30 51 C0 00			//Left/Right ADCs powered up; Left/Right ADCs unmuted
w 30 00 00			//Page 0
w 30 57 9E 2E 50 00 0C 03	//AGC configuration
w 30 56 C2			//AGC configuration