w 30 00 00 # Page 0
w 30 01 01 # Reset
w 30 04 07 # BCLK = 2.304MHz as PLL_INPUT; PLL_CLK selected
w 30 05 91 # PLL on; P = 1; R = 1
w 30 06 08 # J = 8
w 30 07 00 # D = 0
w 30 08 00
w 30 1b 00 # 16-bits; I2S; BCLK/WCLK as inputs
w 30 1c 02 # Data offset 2 BCLKs
w 30 0b 82 # N = 2
w 30 0c 88 # M = 8
w 30 0d 00 # DOSR = 128
w 30 0e 80
w 30 3c 19 # PRB_P25
w 30 3d 05 # Reserved
w 30 25 90 # Read only register
w 30 00 08 # Page 8
w 30 01 04 # Adaptive filtering
w 30 00 01 # Page 1
w 30 1f 1c # CMV = 1.8V
w 30 2a 04 # Class-D amp not muted, 6dB gain
w 30 20 86 # Class-D amp on
w 30 21 4e # Pop removal settings
w 30 23 40 # DAC routed to the mixer amp
w 30 24 80 # Analog volume routed to HPOUT
w 30 1f 84 # HPOUT on; CMV = 1.35V
w 30 28 06 # HPOUT not muted; 0dB gain
w 30 26 00 # Analog volume routed to Class-D driver
w 30 2e 0b # MICBIAS = AVDD; MICBIAS powered up
w 30 00 00 # Page 0
w 30 3f 96 # DAC on; DAC to left data; Soft-stepping disabled
w 30 40 04 # DAC not muted
w 30 41 00 # DAC gain = 0dB