# sample I2C script
# set interface mode to i2c fast
i i2cfast
# set register page to 0
w e0 7f 00
# port a setup as slave with i2s data format
w e0 03 01
w e0 04 00
# dit setup with port a as the data source
# mclk is selected as the master clock and divided by 512 to set the output frame rate
# block start is an output and valid audio data is indicated by the v bit
# the v bit source is the valid bit in control register 0x07
# c and u data are sourced from the data buffers on register page 2
w e0 07 64
w e0 08 00
w e0 09 01
# dir setup with rxcki as the ref clock and rx1 as the input
# rxcko output is enabled with no clock divider
# audio output data is muted for loss of lock condition
# recovered clock is stopped for loss of lock condition  
w e0 0d 00
w e0 0e 09
# pll1 setup for 24.576mhz rxcki where p is 2 j is 8 d is 0
w e0 0f 22
w e0 10 00
w e0 11 00
# port b setup as master with the dir output and rxcko as the data and master clock source
# data format is i2s and the rxcko is divided by 512
w e0 05 29
w e0 06 0b
# set gpo1 to dir block start clock output 
w e0 1b 0a
# set gpo2 to dir sync clock output
w e0 1c 0e
# set gpo3 to dir channel status data serial output
w e0 1d 08
# set gpo3 to dir user data serial output
w e0 1e 09
# power up all blocks except the src
w e0 01 3e
# disable dit c and u buffer transfers
w e0 08 08
# set register page to 2
w e0 7f 02
# set dit channel status data for bytes 0 thru 2
# professional mode with pcm audio no emphasis locked 48khz sampling freq 
# all other channel status bytes are set to default 0x00 value
w e0 00 81
w e0 01 81
w e0 02 10
w e0 03 10
w e0 04 34
w e0 05 34
# set register page to 0
w e0 7f 00
# enable dit c and u buffer transfers
w e0 08 00
b
# dit and port b setup for 96k input and output
w e0 06 09
w e0 07 24
w e0 08 08
w e0 7f 02
w e0 00 80
w e0 01 80
w e0 08 08
w e0 09 08
w e0 7f 00
w e0 08 00
b
# dit and port b setup for 192k input and output
w e0 06 08
w e0 07 04
w e0 08 08
w e0 7f 02
w e0 00 80
w e0 01 80
w e0 08 18
w e0 09 18
w e0 7f 00
w e0 08 00