# program memory
    w 94 00 00 #		
    w 94 7f 00 #		Switch to Book 0
    w 94 02 11 #		PowerDown DSP
    w 94 01 11 #		Reset module & registers. Bits are auto cleared
    d 3125 #			Wait 100 ms
    w 94 03 11 #		Mute L&R
    w 94 2a 00 #		Zero Data path L&R (= mute...)
    w 94 25 18 #		Ignore MCLK error detection
    w 94 0d 00 #		Clck config..
    w 94 02 00 #		Wake up DSP
# Sample rate update
    w 94 02 80 #		Reset DSP
# speed 03-48k 04-96k
# dynamically reading speed
    w 94 22 03 #		Set FS Speed. Ignored in auto clock mode	
    w 94 02 00 #		Restart DSP
# write coefficients of various components
    w 94 00 00 #
    w 94 7f 8c #		Switch to Book8c
#    w 94 00 1e #
#    w 94 44 00 80 00 00 #	Vol-L to 0dB (default setting)
#    w 94 48 00 80 00 00 #	Vol-R to 0dB (default setting)
    w 94 00 15 #		Page 15
    w 94 58 3f 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00 #	BQ1-L -6dB
    w 94 00 18 #		Page 18
    w 94 18 7f 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00 #	BQ1-R 0dB
# swap command
    w 94 00 00 #		
    w 94 7f 8c #		Switch to Book8c
    w 94 00 23 #		Goto Page 23
    w 94 14 00 00 00 01 #	Write 00 00 00 01 in reg 14-17
# register tuning
    w 94 00 00 #		
    w 94 7f 00 #		Switch to Book0
    w 94 00 01 #		Switch to Page1
    w 94 02 00 #		Analog Gain set to 0dB	
    w 94 06 01 #		Analog mute follows digital mute	
# Unmute the device
    w 94 00 00 #		Switch to Page0
    w 94 03 00 #		UnMute L&R	
    w 94 2a 11 #		Enable data path (L-L & R-R)