main()
{

//
    delay_cycles(70400);  		//wait for POST operation

    SYSCFG_DL_init();    		// init all gpio and spi with spi mode 1

    delay_cycles(32000);  		//required min 20ns we provide 1ms delay

    regWrite(REF_ADDR_MASK,0x3A);
    delay_cycles(32000);
    regRead(REF_ADDR_MASK);

    regWrite(PGA_ADDR_MASK,0x0A);       
    delay_cycles(32000);
    regRead(PGA_ADDR_MASK);

    regWrite(INPMUX_ADDR_MASK,0x12);
    delay_cycles(32000);
    regRead(INPMUX_ADDR_MASK);

    regWrite(IDACMAG_ADDR_MASK,0x07);    //07// IDAC magnitude set to 1mA
    delay_cycles(32000);
    regRead(IDACMAG_ADDR_MASK);

    regWrite(DATARATE_ADDR_MASK,0x14);
    delay_cycles(32000);
    regRead(DATARATE_ADDR_MASK);

    regWrite(SYS_ADDR_MASK,0x10);
    delay_cycles(32000);
    regRead(SYS_ADDR_MASK);

    regWrite(IDACMUX_ADDR_MASK,0x35);
    delay_cycles(32000);
    regRead(IDACMUX_ADDR_MASK);

    readRegs(ID_ADDR_MASK,18,Data);
    delay_cycles(32000);
    regRead(ID_ADDR_MASK);
}


/////////////////////////////////////////////////
void regWrite(unsigned int regnum, unsigned char data)
{
    uint8_t ulDataTx[3];
    ulDataTx[0] = REGWR_OPCODE_MASK + (regnum & 0x1f);
    ulDataTx[1] = 0x00;
    ulDataTx[2] = data;
    for(int i=0;i<3;i++)
    {
        DL_SPI_transmitData8(SPI_0_INST,ulDataTx[i]);
    }
}
////////////////////////////////////////////////////////

void readRegs(unsigned int regnum, unsigned int count, uint8_t *data)
{
    int i;
    uint8_t ulDataTx[2];

    ulDataTx[0] = REGRD_OPCODE_MASK + (regnum & 0x1f);
    ulDataTx[1] = count-1;
    transfer(ulDataTx[0]);
    transfer(ulDataTx[1]);
    for(i = 0; i <= count; i++)
    {
        data[i] = transfer(0);
        if(regnum+i < NUM_REGISTERS)
            registers[regnum+i] = data[i];
    }
}
///////////////////////////////////////////////////////////
uint8_t transfer(uint8_t tx)
{
    uint8_t rx;
    /* Set up data for the next xmit */
    DL_SPI_transmitData8(SPI_0_INST,tx);
    /* Wait for data to appear */
    rx= DL_SPI_receiveDataBlocking8(SPI_0_INST);
   // rx= DL_SPI_receiveDataBlocking32(SPI_0_INST);
    return rx;
}