From e6fef5f57d8cc5582ddf906befe84ae9c786bc78 Mon Sep 17 00:00:00 2001 From: xujinmin Date: Wed, 15 Feb 2023 16:18:00 +0800 Subject: [PATCH] add phy tja1101 Change-Id: I100fa17ce35a1b9d76644d5195f4d0693b76c0d2 --- psdkra/ethfw/ethfw/src/ethfw.c | 0 .../utils/board/src/j721e/board_j721e_evm.c | 52 +++-- .../utils/intervlan/src/eth_hwintervlan.c | 1 + .../board/src/j721e_evm/J721E_pinmux_data.c | 6 +- .../j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c | 155 +++++++++++-- .../src/j721e_evm/board_ethernet_config.c | 7 +- .../packages/ti/drv/enet/enet_cfg.h | 2 +- .../ti/drv/enet/include/phy/tja1101.h | 104 +++++++++ .../ti/drv/enet/soc/j7x/j721e/enet_soc.c | 2 +- .../packages/ti/drv/enet/src/phy/enetphy.c | 22 +- .../packages/ti/drv/enet/src/phy/makefile | 2 +- .../packages/ti/drv/enet/src/phy/tja1101.c | 212 ++++++++++++++++++ .../ti/drv/enet/src/phy/tja1101_priv.h | 94 ++++++++ .../platform/j721e/rtos/common/app_init.c | 2 +- .../utils/ethfw/src/app_ethfw_freertos.c | 36 +-- .../vision_apps/utils/ethfw/src/concerto.mak | 2 +- 16 files changed, 628 insertions(+), 71 deletions(-) mode change 100644 => 100755 psdkra/ethfw/ethfw/src/ethfw.c mode change 100644 => 100755 psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c create mode 100755 psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/include/phy/tja1101.h mode change 100644 => 100755 psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c create mode 100755 psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/tja1101.c create mode 100755 psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/tja1101_priv.h diff --git a/psdkra/ethfw/ethfw/src/ethfw.c b/psdkra/ethfw/ethfw/src/ethfw.c old mode 100644 new mode 100755 diff --git a/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c b/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c old mode 100644 new mode 100755 index d547a8773c..dfc21e61c2 --- a/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c +++ b/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c @@ -191,8 +191,8 @@ extern pinmuxBoardCfg_t gEthFwPinmuxData[]; /* GPIO Driver board specific pin configuration structure */ GPIO_PinConfig gEthFw_gpioPinCfgs[] = { - GPIO_DEVICE_CONFIG(0, 61) | GPIO_CFG_OUTPUT, - GPIO_DEVICE_CONFIG(0, 62) | GPIO_CFG_OUTPUT, + GPIO_DEVICE_CONFIG(0, 41) | GPIO_CFG_OUTPUT, + GPIO_DEVICE_CONFIG(0, 44) | GPIO_CFG_OUTPUT, }; /* GPIO Driver callback functions */ @@ -235,7 +235,7 @@ static const Dp83867_Cfg gEnetGesiBoard_dp83867PhyCfg = /* 4 x RGMII ports in GESI expansion board */ static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] = { - { /* "PRG1_RGMII1_B" */ + /*{ [> "PRG1_RGMII1_B" <] .macPort = ENET_MAC_PORT_1, .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, .phyCfg = @@ -248,8 +248,8 @@ static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] = }, .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID, .linkCfg = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO }, - }, - { /* "PRG1_RGMII2_T" */ + },*/ + /*{ [> "PRG1_RGMII2_T" <] .macPort = ENET_MAC_PORT_8, .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, .phyCfg = @@ -262,8 +262,8 @@ static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] = }, .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID, .linkCfg = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO }, - }, - { /* "PRG0_RGMII1_B" */ + },*/ + /*{ [> "PRG0_RGMII1_B" <] .macPort = ENET_MAC_PORT_3, .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, .phyCfg = @@ -276,20 +276,22 @@ static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] = }, .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID, .linkCfg = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO }, - }, + },*/ { /* "PRG0_RGMII02_T" */ - .macPort = ENET_MAC_PORT_4, - .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED }, + .macPort = ENET_MAC_PORT_1, + .mii = { ENET_MAC_LAYER_MII, ENET_MAC_SUBLAYER_REDUCED }, .phyCfg = { - .phyAddr = 3U, + .phyAddr = 4U, .isStrapped = false, .skipExtendedCfg = false, - .extendedCfg = &gEnetGesiBoard_dp83867PhyCfg, - .extendedCfgSize = sizeof(gEnetGesiBoard_dp83867PhyCfg), + //.extendedCfg = &gEnetGesiBoard_dp83867PhyCfg, + //.extendedCfgSize = sizeof(gEnetGesiBoard_dp83867PhyCfg), + .extendedCfg = NULL, + .extendedCfgSize = 0U, }, - .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID, - .linkCfg = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO }, + //.sgmiiMode = ENET_MAC_SGMIIMODE_INVALID, + .linkCfg = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO }, }, }; @@ -379,7 +381,7 @@ int32_t EthFwBoard_init(uint32_t flags) { Board_initCfg boardCfg = 0U; Board_STATUS boardStatus; - + /* Save the functionality requested by app */ gEthFwBoard.enetBridgeEnabled = ENET_NOT_ZERO(flags & ETHFW_BOARD_ENET_BRIDGE_ENABLE); gEthFwBoard.gesiEnabled = ENET_NOT_ZERO(flags & ETHFW_BOARD_GESI_ENABLE); @@ -581,7 +583,7 @@ static void EthFwBoard_configPinmux(void) Board_pinmuxUpdate(gEthFwPinmuxData, BOARD_SOC_DOMAIN_MAIN); /* Configure pinmux settings for Ethernet ports and MDIO */ - Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9gQsgmii, BOARD_SOC_DOMAIN_MAIN); + Board_pinmuxUpdate( gJ721E_MainPinmuxDataGesiCpsw9g, BOARD_SOC_DOMAIN_MAIN); /* REVISIT - Configure CPSW9G pins for ports on the GESI board */ Board_pinmuxGetCfg(&pinmuxCfg); @@ -604,7 +606,7 @@ static void EthFwBoard_detectDBs(void) { /* Assume expansion boards are present if detection not allowed */ gEthFwBoard.gesiDetected = true; - gEthFwBoard.qenetDetected = true; + gEthFwBoard.qenetDetected = false; } } @@ -621,12 +623,16 @@ static void EthFwBoard_configUart(void) static void EthFwBoard_configGesi(void) { - if (gEthFwBoard.gpioAllowed) - { + int i=0; + /*if (gEthFwBoard.gpioAllowed) + {*/ GPIO_init(); - GPIO_write(0, 1); - GPIO_write(1, 1); - } + GPIO_write(0, 0); + appLogWaitMsecs(200); + GPIO_write(0, 1); + appLogWaitMsecs(50); + GPIO_write(1, 1); + /*}*/ } static void EthFwBoard_configQenet(void) diff --git a/psdkra/ethfw/utils/intervlan/src/eth_hwintervlan.c b/psdkra/ethfw/utils/intervlan/src/eth_hwintervlan.c index e7928c2839..b94bd2ab26 100644 --- a/psdkra/ethfw/utils/intervlan/src/eth_hwintervlan.c +++ b/psdkra/ethfw/utils/intervlan/src/eth_hwintervlan.c @@ -197,6 +197,7 @@ void EthHwInterVlan_setOpenPrms(Cpsw_Cfg *pCpswCfg) pCpswCfg->aleCfg.policerGlobalCfg.yellowDropEn = FALSE; pCpswCfg->aleCfg.policerGlobalCfg.policerNoMatchMode = CPSW_ALE_POLICER_NOMATCH_MODE_GREEN; pCpswCfg->aleCfg.vlanCfg.aleVlanAwareMode = TRUE; + /*pCpswCfg->aleCfg.vlanCfg.aleVlanAwareMode = FALSE;*/ pCpswCfg->aleCfg.vlanCfg.cpswVlanAwareMode = TRUE; pCpswCfg->aleCfg.vlanCfg.unknownVlanMemberListMask = 0; diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c index 72f8646960..5b1e7a92d9 100755 --- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c @@ -458,10 +458,10 @@ static pinmuxPerCfg_t gMcu_fss0_ospi0PinCfg[] = static pinmuxPerCfg_t gMcu_fss0_ospi1PinCfg[] = { /* MyMCU_OSPI1 -> MCU_OSPI1_CLK -> F22 */ - { + /*{ PIN_MCU_OSPI1_CLK, PIN_MODE(0) | \ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) - }, + },*/ /* MyMCU_OSPI1 -> MCU_OSPI1_CSn0 -> C22 */ { PIN_MCU_OSPI1_CSN0, PIN_MODE(0) | \ @@ -503,7 +503,7 @@ static pinmuxPerCfg_t gMcu_fss0_ospi1PinCfg[] = static pinmuxModuleCfg_t gMcu_fss0_ospiPinCfg[] = { {0, TRUE, gMcu_fss0_ospi0PinCfg}, - {1, TRUE, gMcu_fss0_ospi1PinCfg}, + {1, FALSE, gMcu_fss0_ospi1PinCfg}, {PINMUX_END} }; diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c index 28c8035026..3cf3b3cd90 100755 --- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c @@ -39,14 +39,15 @@ static pinmuxModuleCfg_t gCpsw9gPinCfg[] = static pinmuxPerCfg_t gGpio0PinCfg[] = { - /* MyGPIO0 -> GPIO0_96 -> T23 */ + /* MyGPIO1 -> GPIO0_41 -> AD19 */ { - PIN_RGMII5_RD0, PIN_MODE(7) | \ + PIN_PRG1_MDIO0_MDIO, PIN_MODE(7) | \ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) }, - /* MyGPIO0 -> GPIO0_104 -> W26 */ + + /* MyGPIO1 -> GPIO0_44 -> AE28 */ { - PIN_RGMII6_RXC, PIN_MODE(7) | \ + PIN_PRG0_PRU0_GPO1, PIN_MODE(7) | \ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) }, {PINMUX_END} @@ -61,16 +62,16 @@ static pinmuxModuleCfg_t gGpioPinCfg[] = static pinmuxPerCfg_t gMdio0PinCfg[] = { - /* MyMDIO1 -> MDIO0_MDC -> V24 */ - { - PIN_MDIO0_MDC, PIN_MODE(0) | \ - ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) - }, /* MyMDIO1 -> MDIO0_MDIO -> V26 */ { PIN_MDIO0_MDIO, PIN_MODE(0) | \ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) }, + /* MyMDIO1 -> MDIO0_MDC -> V24 */ + { + PIN_MDIO0_MDC, PIN_MODE(0) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + }, {PINMUX_END} }; @@ -146,6 +147,125 @@ static pinmuxPerCfg_t gRgmii3PinCfg[] = {PINMUX_END} }; +static pinmuxPerCfg_t gRmii1PinCfg[] = +{ + /* MyRMII1 -> RMII1_CRS_DV -> AF22 */ + { + PIN_PRG1_PRU0_GPO2, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + /* MyRMII1 -> RMII1_RXD0 -> AC23 */ + { + PIN_PRG1_PRU0_GPO0, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + /* MyRMII1 -> RMII1_RXD1 -> AG22 */ + { + PIN_PRG1_PRU0_GPO1, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + /* MyRMII1 -> RMII1_RX_ER -> AJ23 */ + { + PIN_PRG1_PRU0_GPO3, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + /* MyRMII1 -> RMII1_TXD0 -> AH23 */ + { + PIN_PRG1_PRU0_GPO4, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + }, + /* MyRMII1 -> RMII1_TXD1 -> AD22 */ + { + PIN_PRG1_PRU0_GPO6, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + }, + /* MyRMII1 -> RMII1_TX_EN -> AD20 */ + { + PIN_PRG1_PRU0_GPO5, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + }, + + { + PIN_PRG1_MDIO0_MDC, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + + {PINMUX_END} +}; + +static pinmuxPerCfg_t gRmii4PinCfg[] = +{ + /* MyRMII1 -> RMII4_CRS_DV -> AD27 */ + { + PIN_PRG0_PRU1_GPO2, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + /* MyRMII1 -> RMII4_RXD0 -> AE29 */ + { + PIN_PRG0_PRU1_GPO0, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + /* MyRMII1 -> RMII4_RXD1 -> AD28 */ + { + PIN_PRG0_PRU1_GPO1, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + /* MyRMII1 -> RMII4_RX_ER -> AC25 */ + { + PIN_PRG0_PRU1_GPO3, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + /* MyRMII1 -> RMII4_TXD0 -> AC26 */ + { + PIN_PRG0_PRU1_GPO6, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + }, + /* MyRMII1 -> RMII4_TXD1 -> AD29 */ + { + PIN_PRG0_PRU1_GPO4, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + }, + /* MyRMII1 -> RMII4_TX_EN -> AG26 */ + { + PIN_PRG0_PRU1_GPO11, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + }, + + + { + PIN_PRG1_MDIO0_MDC, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + }, + + + /* MyRGMII4 -> RGMII4_TD1 -> AF27 */ + /*{ + PIN_PRG0_PRU1_GPO12, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + },*/ + /* MyRGMII4 -> RGMII4_TD2 -> AF26 */ + /*{ + PIN_PRG0_PRU1_GPO13, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + },*/ + /* MyRGMII4 -> RGMII4_TD3 -> AE25 */ + /*{ + PIN_PRG0_PRU1_GPO14, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)) + },*/ + /* MyRGMII4 -> RGMII4_TXC -> AG29 */ + /*{ + PIN_PRG0_PRU1_GPO16, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + },*/ + /* MyRGMII4 -> RGMII4_TX_CTL -> AF29 */ + /*{ + PIN_PRG0_PRU1_GPO15, PIN_MODE(5) | \ + ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)) + },*/ + {PINMUX_END} +}; + static pinmuxPerCfg_t gRgmii4PinCfg[] = { /* MyRGMII4 -> RGMII4_RD0 -> AE29 */ @@ -471,15 +591,23 @@ static pinmuxPerCfg_t gRgmii8PinCfg[] = {PINMUX_END} }; -static pinmuxModuleCfg_t gRgmiiPinCfg[] = +/*static pinmuxModuleCfg_t gRgmiiPinCfg[] = { {3, TRUE, gRgmii3PinCfg}, {4, TRUE, gRgmii4PinCfg}, {1, TRUE, gRgmii1PinCfg}, {2, TRUE, gRgmii2PinCfg}, {PINMUX_END} -}; +};*/ +static pinmuxModuleCfg_t g_MtRgmiiPinCfg[] = +{ + {3, FALSE, gRgmii3PinCfg}, + {4, FALSE, gRmii4PinCfg}, + {1, TRUE, gRmii1PinCfg}, + {2, FALSE, gRgmii2PinCfg}, + {PINMUX_END} +}; static pinmuxModuleCfg_t gSgmiiPinCfg[] = { @@ -563,8 +691,9 @@ pinmuxBoardCfg_t gJ721E_MainPinmuxDataGesiCpsw9g[] = {0, gCpsw9gPinCfg}, {1, gGpioPinCfg}, {2, gMdioPinCfg}, - {3, gRgmiiPinCfg}, - {4, gRmiiPinCfg}, + /*{3, gRgmiiPinCfg},*/ + {3, g_MtRgmiiPinCfg}, + /*{4, gRmiiPinCfg},*/ {PINMUX_END} }; diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/board_ethernet_config.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/board_ethernet_config.c index 575b2e2db5..8fb4422f02 100755 --- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/board_ethernet_config.c +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/board_ethernet_config.c @@ -709,12 +709,9 @@ Board_STATUS Board_ethConfigCpsw9g(void) /* Configures the CPSW9G RGMII ports */ for(portNum=0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++) { - if ( 0U == portNum || - 2U == portNum || - 3U == portNum || - 7U == portNum ) + if ( 0U == portNum ) { - status = Board_cpsw9gEthConfig(portNum, RGMII); + status = Board_cpsw9gEthConfig(portNum, RMII); } else { diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/enet_cfg.h b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/enet_cfg.h index 4e0528f982..276fe85f5b 100644 --- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/enet_cfg.h +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/enet_cfg.h @@ -89,7 +89,7 @@ extern "C" { /* --------------------------------------------------------------------------*/ /*! \brief CPSW Q/SGMII support (requires #ENET_CFG_CPSW_MACPORT_SGMII). */ -#define ENET_CFG_CPSW_SGMII (ENET_ON) +//#define ENET_CFG_CPSW_SGMII (ENET_ON) /*! \brief CPSW interVLAN support support (requires #ENET_CFG_CPSW_MACPORT_INTERVLAN). */ #define ENET_CFG_CPSW_INTERVLAN (ENET_ON) diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/include/phy/tja1101.h b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/include/phy/tja1101.h new file mode 100755 index 0000000000..44aa8273bb --- /dev/null +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/include/phy/tja1101.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) Texas Instruments Incorporated 2020 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * \file tja1101.h + * + * \brief This file contains the type definitions and helper macros for the + * TJA1101 Ethernet PHY. + */ + +/*! + * \ingroup DRV_ENETPHY + * \defgroup ENETPHY_TJA1101 TI TJA1101 PHY + * + * TI TJA1101 RMII Ethernet PHY. + * + * @{ + */ + +#ifndef TJA1101_H_ +#define TJA1101_H_ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* ========================================================================== */ +/* Macros */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Structures and Enums */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Global Variables Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Deprecated Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Static Function Definitions */ +/* ========================================================================== */ + +/* None */ + +#ifdef __cplusplus +} +#endif + +#endif /* TJA1101_H_ */ + +/* @} */ diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c old mode 100644 new mode 100755 index 1ffb840e2f..f67bcf81b1 --- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/soc/j7x/j721e/enet_soc.c @@ -1446,7 +1446,7 @@ int32_t EnetSoc_getMacPortMii(Enet_Type enetType, { EnetMac_LayerType *enetLayer = &mii->layerType; EnetMac_SublayerType *enetSublayer = &mii->sublayerType; - uint32_t modeSel = CPSW_ENET_CTRL_MODE_RGMII; + uint32_t modeSel = CPSW_ENET_CTRL_MODE_RMII; int32_t status = ENET_EFAIL; switch (enetType) diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/enetphy.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/enetphy.c index 43a70bc5b5..70a5751637 100644 --- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/enetphy.c +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/enetphy.c @@ -179,6 +179,7 @@ extern EnetPhy_Drv gEnetPhyDrvGeneric; extern EnetPhy_Drv gEnetPhyDrvDp83822; extern EnetPhy_Drv gEnetPhyDrvDp83867; extern EnetPhy_Drv gEnetPhyDrvVsc8514; +extern EnetPhy_Drv gEnetPhyDrvTja1101; /*! \brief All the registered PHY specific drivers. */ static EnetPhyDrv_Handle gEnetPhyDrvs[] = @@ -186,6 +187,7 @@ static EnetPhyDrv_Handle gEnetPhyDrvs[] = &gEnetPhyDrvVsc8514, /* VSC8514 */ &gEnetPhyDrvDp83822, /* DP83822 */ &gEnetPhyDrvDp83867, /* DP83867 */ + &gEnetPhyDrvTja1101, /*TJA1101 */ &gEnetPhyDrvGeneric, /* Generic PHY - must be last */ }; @@ -943,9 +945,18 @@ static void EnetPhy_initState(EnetPhy_Handle hPhy) { EnetPhy_State *state = &hPhy->state; - state->speed = ENETPHY_SPEED_10MBIT; - state->duplexity = ENETPHY_DUPLEX_HALF; - state->phyLinkCaps = 0U; + if(hPhy->addr == 4) + { + state->speed = ENETPHY_SPEED_100MBIT; + state->duplexity = ENETPHY_DUPLEX_FULL; + state->phyLinkCaps = 0U; + } + else + { + state->speed = ENETPHY_SPEED_10MBIT; + state->duplexity = ENETPHY_DUPLEX_HALF; + state->phyLinkCaps = 0U; + } if (hPhy->phyCfg.isStrapped) { @@ -1088,7 +1099,10 @@ static void EnetPhy_enableState(EnetPhy_Handle hPhy) ENETTRACE_DBG("PHY %u: req caps: %s\n", hPhy->addr, EnetPhy_getCapsString(hPhy->reqLinkCaps)); - state->phyLinkCaps = EnetPhy_getLocalCaps(hPhy); + if(hPhy->addr == 4) + state->phyLinkCaps = ENETPHY_LINK_CAP_FD100; + else + state->phyLinkCaps = EnetPhy_getLocalCaps(hPhy); ENETTRACE_DBG("PHY %u: PHY caps: %s\n", hPhy->addr, EnetPhy_getCapsString(state->phyLinkCaps)); diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/makefile b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/makefile index f4c3b72336..f6715cfb22 100644 --- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/makefile +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/makefile @@ -19,7 +19,7 @@ INCLUDE_INTERNAL_INTERFACES = # Common source files and CFLAGS across all platforms and cores SRCS_COMMON += enetphy.c generic_phy.c -SRCS_COMMON += dp83867.c dp83822.c vsc8514.c +SRCS_COMMON += dp83867.c dp83822.c vsc8514.c tja1101.c PACKAGE_SRCS_COMMON = $(SRCDIR) CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(ENET_CFLAGS) diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/tja1101.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/tja1101.c new file mode 100755 index 0000000000..1e532e57c2 --- /dev/null +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/tja1101.c @@ -0,0 +1,212 @@ +/* + * Copyright (c) Texas Instruments Incorporated 2020 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * \file tja1101.c + * + * \brief This file contains the implementation of the TJA1101 PHY. + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include +#include +#include +#include +#include +#include "enetphy_priv.h" +#include "generic_phy.h" +#include "tja1101_priv.h" + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +#define TJA1101_OUI (0x6037U) +#define TJA1101_MODEL (0x10U) +#define TJA1101_REV (0x2U) + +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ + +static bool Tja1101_isPhyDevSupported(EnetPhy_Handle hPhy, + const EnetPhy_Version *version); + +static bool Tja1101_isMacModeSupported(EnetPhy_Handle hPhy, + EnetPhy_Mii mii); + +static int32_t Tja1101_config(EnetPhy_Handle hPhy, + const EnetPhy_Cfg *cfg, + EnetPhy_Mii mii); + +void Tja1101_reset(EnetPhy_Handle hPhy); + +bool Tja1101_isResetComplete(EnetPhy_Handle hPhy); + +static void Tja1101_printRegs(EnetPhy_Handle hPhy); + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +EnetPhy_Drv gEnetPhyDrvTja1101 = +{ + .name = "tja1101", + .isPhyDevSupported = Tja1101_isPhyDevSupported, + .isMacModeSupported = Tja1101_isMacModeSupported, + .config = Tja1101_config, + .reset = Tja1101_reset, + .isResetComplete = Tja1101_isResetComplete, + .readExtReg = GenericPhy_readExtReg, + .writeExtReg = GenericPhy_writeExtReg, + .printRegs = Tja1101_printRegs, +}; + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +static bool Tja1101_isPhyDevSupported(EnetPhy_Handle hPhy, + const EnetPhy_Version *version) +{ + bool supported = false; + + if ((version->oui == TJA1101_OUI) && + (version->model == TJA1101_MODEL) && + (version->revision == TJA1101_REV)) + { + supported = true; + } + + return supported; +} + +static bool Tja1101_isMacModeSupported(EnetPhy_Handle hPhy, + EnetPhy_Mii mii) +{ + bool supported; + + switch (mii) + { + case ENETPHY_MAC_MII_RMII: + supported = true; + break; + + /* This driver doesn't support MII and RGMII interfaces, + * but the TJA1101 PHY does support them */ + case ENETPHY_MAC_MII_MII: + case ENETPHY_MAC_MII_RGMII: + default: + supported = false; + break; + } + + return supported; +} + +static int32_t Tja1101_config(EnetPhy_Handle hPhy, + const EnetPhy_Cfg *cfg, + EnetPhy_Mii mii) +{ + uint16_t i; + int32_t status = ENETPHY_SOK; + uint16_t val; + +#if 1 + if(hPhy->addr == 4) + { + /* enable the register RW */ + EnetPhy_writeReg(hPhy, 17, 0x9804); + + /* RMII mode enabled (50 MHz input on REF_CLK) */ + EnetPhy_writeReg(hPhy, 18, 0xDE05); + + /* 50 MHz input at REF_CLK; RMII mode only; no XTAL; no clock at CLK_IN_OUT */ + EnetPhy_readReg(hPhy, 27, &val); + val &= ~(3 << 12); + EnetPhy_writeReg(hPhy, 27, val); + } +#else + // not do anything +#endif + /*if( hPhy->addr == 4 ) + { + for(i = 0; i <= 28; i++) + { + EnetPhy_readReg(hPhy, i, &val); + [>ENETTRACE_DBG("PHY %u: register%u = 0x%04x\n", hPhy->addr, i, val);<] + EnetUtils_printf("PHY %u: register%u = 0x%04x\n", hPhy->addr, i, val); + } + }*/ + + return status; +} + +void Tja1101_reset(EnetPhy_Handle hPhy) +{ + ENETTRACE_DBG("PHY %u: reset\n", hPhy->addr); + EnetPhy_writeReg(hPhy, 17, 0x9804); + /* Reset the PHY */ + EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_RESET, BMCR_RESET); +} + +bool Tja1101_isResetComplete(EnetPhy_Handle hPhy) +{ + bool complete = true; + + ENETTRACE_DBG("PHY %u: reset is %scomplete\n", hPhy->addr, complete ? "" : "not"); + + return complete; +} + +static void Tja1101_printRegs(EnetPhy_Handle hPhy) +{ + uint32_t phyAddr = hPhy->addr; + uint16_t val = 0; + EnetPhy_readReg(hPhy, PHY_BMCR, &val); + EnetUtils_printf("PHY %u: BMCR = 0x%04x\n", phyAddr, val); + EnetPhy_readReg(hPhy, PHY_BMSR, &val); + EnetUtils_printf("PHY %u: BMSR = 0x%04x\n", phyAddr, val); + EnetPhy_readReg(hPhy, PHY_PHYIDR1, &val); + EnetUtils_printf("PHY %u: PHYIDR1 = 0x%04x\n", phyAddr, val); + EnetPhy_readReg(hPhy, PHY_PHYIDR2, &val); + EnetUtils_printf("PHY %u: PHYIDR2 = 0x%04x\n", phyAddr, val); +} diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/tja1101_priv.h b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/tja1101_priv.h new file mode 100755 index 0000000000..ab504a5896 --- /dev/null +++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/tja1101_priv.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) Texas Instruments Incorporated 2020 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * \file tja1101_priv.h + * + * \brief This file contains private type definitions and helper macros for the + * TJA1101 Ethernet PHY. + */ + +#ifndef TJA1101_PRIV_H_ +#define TJA1101_PRIV_H_ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include +#include "enetphy_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* ========================================================================== */ +/* Macros */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Structures and Enums */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Global Variables Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Deprecated Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Static Function Definitions */ +/* ========================================================================== */ + +/* None */ + +#ifdef __cplusplus +} +#endif + +#endif /* TJA1101_PRIV_H_ */ diff --git a/psdkra/vision_apps/platform/j721e/rtos/common/app_init.c b/psdkra/vision_apps/platform/j721e/rtos/common/app_init.c index 0e438b4e67..a2371108a4 100755 --- a/psdkra/vision_apps/platform/j721e/rtos/common/app_init.c +++ b/psdkra/vision_apps/platform/j721e/rtos/common/app_init.c @@ -511,7 +511,7 @@ int32_t appInit() #endif #endif - #if 0 //def ENABLE_ETHFW + #ifdef ENABLE_ETHFW status = appEthFwInit(); APP_ASSERT_SUCCESS(status); status = appEthFwRemoteServerInit(); diff --git a/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c b/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c index cc484978a7..9e0807bfa2 100644 --- a/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c +++ b/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c @@ -129,10 +129,10 @@ static Enet_MacPort gEthAppPorts[] = #if defined(SOC_J721E) /* On J721E EVM to use all 8 ports simultaneously, we use below configuration RGMII Ports - 1,3,4,8. QSGMII ports - 2,5,6,7 */ + /*ENET_MAC_PORT_1, [> RGMII <]*/ + /*ENET_MAC_PORT_3, [> RGMII <]*/ ENET_MAC_PORT_1, /* RGMII */ - ENET_MAC_PORT_3, /* RGMII */ - ENET_MAC_PORT_4, /* RGMII */ - ENET_MAC_PORT_8, /* RGMII */ + /*ENET_MAC_PORT_8, [> RGMII <]*/ #if defined(ENABLE_QSGMII_PORTS) ENET_MAC_PORT_2, /* QSGMII main */ ENET_MAC_PORT_5, /* QSGMII sub */ @@ -149,22 +149,22 @@ static Enet_MacPort gEthAppPorts[] = static EthFw_VirtPortCfg gEthApp_virtPortCfg[] = { + /*{ + .remoteCoreId = IPC_MPU1_0, + .portId = ETHREMOTECFG_SWITCH_PORT_0, + },*/ + /*{*/ + /*.remoteCoreId = IPC_MCU2_1,*/ + /*.portId = ETHREMOTECFG_SWITCH_PORT_1,*/ + /*},*/ { .remoteCoreId = IPC_MPU1_0, - .portId = ETHREMOTECFG_SWITCH_PORT_0, - }, - { - .remoteCoreId = IPC_MCU2_1, - .portId = ETHREMOTECFG_SWITCH_PORT_1, - }, - { - .remoteCoreId = IPC_MPU1_0, - .portId = ETHREMOTECFG_MAC_PORT_1, - }, - { - .remoteCoreId = IPC_MCU2_1, - .portId = ETHREMOTECFG_MAC_PORT_4, + .portId = ETHREMOTECFG_MAC_PORT_1, }, + /*{*/ + /*.remoteCoreId = IPC_MCU2_1,*/ + /*.portId = ETHREMOTECFG_MAC_PORT_4,*/ + /*},*/ }; static EthFw_VirtPortCfg gEthApp_autosarVirtPortCfg[] = @@ -678,8 +678,8 @@ static void EthApp_netifStatusCb(struct netif *netif) appLogPrintf("Added interface '%c%c%d', IP is %s\n", netif->name[0], netif->name[1], netif->num, ip4addr_ntoa(ipAddr)); - - if (ipAddr->addr != 0) + appLogPrintf("ipaddr->addr=%d\n",ipAddr->addr); + if (ipAddr->addr != 0) { gEthAppObj.hostIpAddr = lwip_ntohl(ip_addr_get_ip4_u32(ipAddr)); diff --git a/psdkra/vision_apps/utils/ethfw/src/concerto.mak b/psdkra/vision_apps/utils/ethfw/src/concerto.mak index 050bc04de0..ddb6afc0f4 100644 --- a/psdkra/vision_apps/utils/ethfw/src/concerto.mak +++ b/psdkra/vision_apps/utils/ethfw/src/concerto.mak @@ -28,7 +28,7 @@ ifeq ($(TARGET_OS),FREERTOS) ifeq ($(ETHFW_INTERCORE_ETH_SUPPORT),yes) DEFS += ETHAPP_ENABLE_INTERCORE_ETH endif - DEFS += ENABLE_QSGMII_PORTS + #DEFS += ENABLE_QSGMII_PORTS endif include $(FINALE) -- 2.17.1