// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
 */

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/sound/ti-mcasp.h>
#include <dt-bindings/net/ti-dp83867.h>

/ {
	chosen {
		stdout-path = "serial9:115200n8";
		bootargs = "console=ttyS9,115200n8 earlycon=ns16550a,mmio32,0x02870000";
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;

		sw10: sw10 {
			label = "GPIO Key USER1";
			linux,code = <BTN_0>;
			gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
		};

		sw11: sw11 {
			label = "GPIO Key USER2";
			linux,code = <BTN_1>;
			gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
		};
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LMS140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	/* Used for 48KHz family */
	pll4: pll4_fixed {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <1179648000>;
	};

	/* Used for 44.1KHz family */
	pll15: pll15_fixed {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <1083801600>;
	};

	sound0: sound@0 {
		compatible = "ti,j721e-cpb-audio";
		ti,model = "j721e-cpb-analog";

		ti,cpb-mcasp = <&mcasp10>;
		ti,cpb-codec = <&pcm3168a_1>;

		clocks = <&pll4>, <&pll15>,
			 <&k3_clks 184 1>,
			 <&k3_clks 184 2>, <&k3_clks 184 4>,
			 <&k3_clks 157 371>,
			 <&k3_clks 157 400>, <&k3_clks 157 401>;
		clock-names = "pll4", "pll15",
			      "cpb-mcasp",
			      "cpb-mcasp-48000", "cpb-mcasp-44100",
			      "audio-refclk2",
			      "audio-refclk2-48000", "audio-refclk2-44100";
	};

	vdd_mmc1: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv_alt: gpio-regulator-TLV71033 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
		regulator-name = "tlv71033";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0
			  3300000 0x1>;
	};

	cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethswitch-device-0";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			/* local-mac-address = [0 0 0 0 0 0]; */
		};
	};

	dp0: connector {
		compatible = "dp-connector";
		label = "DP0";

		port {
			dp_connector_in: endpoint {
				remote-endpoint = <&dp_bridge_output>;
			};
		};
	};
};

&main_pmx0 {
	sw10_button_pins_default: sw10_button_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
		>;
	};

	dp0_pins_default: dp0_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
		>;
	};

	main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
		>;
	};

	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
		>;
	};

	main_i2c6_pins_default: main-i2c6-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
			J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
		>;
	};

	vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
		>;
	};

	main_usbss0_pins_default: main_usbss0_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
		>;
	};

	main_usbss1_pins_default: main_usbss1_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
		>;
	};

	/* Pointing to IVP HW */
	uart0_backplane_coex61_pins_default: uart0_backplane_coex61_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x4, PIN_INPUT, 14) /* (AC23) PRG1_PRU0_GPO0.UART0_RXD */
			J721E_IOPAD(0x8, PIN_OUTPUT, 14) /* (AG22) PRG1_PRU0_GPO1.UART0_TXD */
		>;
	};

	/* Pointing to IVP HW */
	uart1_backplane_coex60_pins_default: uart1_backplane_coex60_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xc, PIN_INPUT, 14) /* (AF22) PRG1_PRU0_GPO2.UART1_RXD */
			J721E_IOPAD(0x10, PIN_OUTPUT, 14) /* (AJ23) PRG1_PRU0_GPO3.UART1_TXD */
		>;
	};

	/* Pointing to IVP HW */
	uart2_bckplane_coex70_pins_default: uart2_bckplane_coex70_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x14, PIN_INPUT, 14) /* (AH23) PRG1_PRU0_GPO4.UART2_RXD */
			J721E_IOPAD(0x1c, PIN_OUTPUT, 14) /* (AD22) PRG1_PRU0_GPO6.UART2_TXD */
		>;
	};



	/* Pointing to IVP HW */
	uart3_backplane_rif0_pins_default: uart3_backplane_rif0_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xb8, PIN_INPUT, 8) /* (AE27) PRG0_PRU0_GPO2.UART3_RXD */
			J721E_IOPAD(0xbc, PIN_OUTPUT, 8) /* (AD26) PRG0_PRU0_GPO3.UART3_TXD */
		>;
	};

	/* Pointing to IVP HW */
	uart4_backplane_rif1_pins_default: uart4_backplane_rif1_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xe8, PIN_INPUT, 8) /* (AG28) PRG0_PRU0_GPO14.UART4_RXD */
			J721E_IOPAD(0xec, PIN_OUTPUT, 8) /* (AG27) PRG0_PRU0_GPO15.UART4_TXD */
		>;
	};

	/* Pointing to IVP HW */
	uart6_switch_mgmt_pins_default: uart6_switch_mgmt_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x210, PIN_INPUT, 1) /* (W3) MCAN1_RX.UART6_CTSn */
			J721E_IOPAD(0x214, PIN_OUTPUT, 1) /* (V4) MCAN1_TX.UART6_RTSn */
			J721E_IOPAD(0x218, PIN_INPUT, 8) /* (W2) I3C0_SCL.UART6_RXD */
			J721E_IOPAD(0x21c, PIN_OUTPUT, 8) /* (W1) I3C0_SDA.UART6_TXD */
		>;
	};

	/* Pointing to IVP HW */
	uart7_ftdi_pins_default: uart7_ftdi_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x248, PIN_INPUT, 1) /* (P24) MMC1_DAT1.UART7_CTSn */
			J721E_IOPAD(0x24c, PIN_OUTPUT, 1) /* (R24) MMC1_DAT0.UART7_RTSn */
			J721E_IOPAD(0x240, PIN_INPUT, 1) /* (R26) MMC1_DAT3.UART7_RXD */
			J721E_IOPAD(0x244, PIN_OUTPUT, 1) /* (R25) MMC1_DAT2.UART7_TXD */
		>;
	};

	/* Pointing to IVP HW */
	uart8_backplane_coex71_pins_default: uart8_backplane_coex71_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x124, PIN_INPUT, 14) /* (Y24) PRG0_PRU1_GPO9.UART8_RXD */
			J721E_IOPAD(0x128, PIN_OUTPUT, 14) /* (AA25) PRG0_PRU1_GPO10.UART8_TXD */
		>;
	};

	/* Pointing to IVP HW */
	i2c1_msp_pins_default: i2c1_msp_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
		>;
	};

	/* Pointing to IVP HW */
	i2c3_des_pins_default: i2c3_des_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
		>;
	};

	/* Pointing to IVP HW */
	i2c4_audio_adc_pins_default: i2c4_audio_adc_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x250, PIN_INPUT_PULLUP, 4) /* (P25) MMC1_CLK.I2C4_SCL */
			J721E_IOPAD(0x254, PIN_INPUT_PULLUP, 4) /* (R29) MMC1_CMD.I2C4_SDA */
		>;
	};

	/* Pointing to IVP HW */
	i2c2_slot7_5_pins_default: i2c2_slot7_5_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c8, PIN_INPUT_PULLUP, 2) /* (AA1) SPI0_CLK.I2C2_SCL */
			J721E_IOPAD(0x1cc, PIN_INPUT_PULLUP, 2) /* (AB5) SPI0_D0.I2C2_SDA */
		>;
	};

	/* Pointing to IVP HW */
	i2c5_avb_clk_pins_default: i2c5_avb_clk_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x260, PIN_INPUT_PULLUP, 4) /* (T28) MMC2_DAT3.I2C5_SCL */
			J721E_IOPAD(0x264, PIN_INPUT_PULLUP, 4) /* (T29) MMC2_DAT2.I2C5_SDA */
		>;
	};

	/* Pointing to IVP HW */
	debug_pins_default: debug_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x158, PIN_OUTPUT, 5) /* (U23) RGMII5_TX_CTL.TRC_CLK */
			J721E_IOPAD(0x15c, PIN_OUTPUT, 5) /* (U26) RGMII5_RX_CTL.TRC_CTL */
			J721E_IOPAD(0x28c, PIN_INPUT, 0) /* (V2) TMS */
			J721E_IOPAD(0x284, PIN_INPUT, 0) /* (V1) TDI */
			J721E_IOPAD(0x288, PIN_OUTPUT, 0) /* (V3) TDO */
			J721E_IOPAD(0x160, PIN_OUTPUT, 5) /* (V28) RGMII5_TD3.TRC_DATA0 */
			J721E_IOPAD(0x164, PIN_OUTPUT, 5) /* (V29) RGMII5_TD2.TRC_DATA1 */
			J721E_IOPAD(0x168, PIN_OUTPUT, 5) /* (V27) RGMII5_TD1.TRC_DATA2 */
			J721E_IOPAD(0x16c, PIN_OUTPUT, 5) /* (U28) RGMII5_TD0.TRC_DATA3 */
			J721E_IOPAD(0x170, PIN_OUTPUT, 5) /* (U29) RGMII5_TXC.TRC_DATA4 */
			J721E_IOPAD(0x174, PIN_OUTPUT, 5) /* (U25) RGMII5_RXC.TRC_DATA5 */
			J721E_IOPAD(0x178, PIN_OUTPUT, 5) /* (U27) RGMII5_RD3.TRC_DATA6 */
			J721E_IOPAD(0x17c, PIN_OUTPUT, 5) /* (U24) RGMII5_RD2.TRC_DATA7 */
			J721E_IOPAD(0x180, PIN_OUTPUT, 5) /* (R23) RGMII5_RD1.TRC_DATA8 */
			J721E_IOPAD(0x184, PIN_OUTPUT, 5) /* (T23) RGMII5_RD0.TRC_DATA9 */
			J721E_IOPAD(0x188, PIN_OUTPUT, 5) /* (Y28) RGMII6_TX_CTL.TRC_DATA10 */
			J721E_IOPAD(0x18c, PIN_OUTPUT, 5) /* (V23) RGMII6_RX_CTL.TRC_DATA11 */
			J721E_IOPAD(0x190, PIN_OUTPUT, 5) /* (W23) RGMII6_TD3.TRC_DATA12 */
			J721E_IOPAD(0x194, PIN_OUTPUT, 5) /* (W28) RGMII6_TD2.TRC_DATA13 */
			J721E_IOPAD(0x198, PIN_OUTPUT, 5) /* (V25) RGMII6_TD1.TRC_DATA14 */
			J721E_IOPAD(0x19c, PIN_OUTPUT, 5) /* (W27) RGMII6_TD0.TRC_DATA15 */
			J721E_IOPAD(0x1a0, PIN_OUTPUT, 5) /* (W29) RGMII6_TXC.TRC_DATA16 */
			J721E_IOPAD(0x1a4, PIN_OUTPUT, 5) /* (W26) RGMII6_RXC.TRC_DATA17 */
			J721E_IOPAD(0x1a8, PIN_OUTPUT, 5) /* (Y29) RGMII6_RD3.TRC_DATA18 */
			J721E_IOPAD(0x1ac, PIN_OUTPUT, 5) /* (Y27) RGMII6_RD2.TRC_DATA19 */
			J721E_IOPAD(0x1b0, PIN_OUTPUT, 5) /* (W24) RGMII6_RD1.TRC_DATA20 */
		>;
	};

	/* Pointing to IVP HW */
	gpio0_pins_default: gpio0_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x24, PIN_INPUT, 7) /* (AJ20) PRG1_PRU0_GPO8.GPIO0_9 */
			J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
			J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
			J721E_IOPAD(0x4c, PIN_INPUT, 7) /* (AJ21) PRG1_PRU0_GPO17.GPIO0_18 */
			J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
			J721E_IOPAD(0x7c, PIN_INPUT, 7) /* (AF21) PRG1_PRU1_GPO9.GPIO0_30 */
			J721E_IOPAD(0xb0, PIN_INPUT, 7) /* (AF28) PRG0_PRU0_GPO0.GPIO0_43 */
			J721E_IOPAD(0xb4, PIN_INPUT, 7) /* (AE28) PRG0_PRU0_GPO1.GPIO0_44 */
			J721E_IOPAD(0xe4, PIN_INPUT, 7) /* (AH29) PRG0_PRU0_GPO13.GPIO0_56 */
			J721E_IOPAD(0xf0, PIN_INPUT, 7) /* (AH28) PRG0_PRU0_GPO16.GPIO0_59 */
			J721E_IOPAD(0x104, PIN_INPUT, 7) /* (AD28) PRG0_PRU1_GPO1.GPIO0_64 */
			J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
			J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
			J721E_IOPAD(0x118, PIN_INPUT, 7) /* (AC26) PRG0_PRU1_GPO6.GPIO0_69 */
			J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
			J721E_IOPAD(0x140, PIN_INPUT, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */
			J721E_IOPAD(0x154, PIN_INPUT, 7) /* (AA27) PRG0_MDIO0_MDC.GPIO0_84 */
			J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
			J721E_IOPAD(0x1e8, PIN_INPUT, 7) /* (AB2) UART0_RXD.GPIO0_121 */
			J721E_IOPAD(0x1f8, PIN_INPUT, 7) /* (AA4) UART1_RXD.GPIO0_125 */
			J721E_IOPAD(0x1fc, PIN_INPUT, 7) /* (AB4) UART1_TXD.GPIO0_126 */
		>;
	};

	/* Pointing to IVP HW */
	gpio1_pins_default: gpio1_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x25c, PIN_INPUT, 7) /* (R28) MMC1_SDWP.GPIO1_22 */
			J721E_IOPAD(0x268, PIN_INPUT, 7) /* (T27) MMC2_DAT1.GPIO1_25 */
			J721E_IOPAD(0x26c, PIN_INPUT, 7) /* (T24) MMC2_DAT0.GPIO1_26 */
			J721E_IOPAD(0x290, PIN_INPUT, 7) /* (U6) USB0_DRVVBUS.GPIO1_29 */
			J721E_IOPAD(0x294, PIN_INPUT, 7) /* (AD1) MLB0_MLBSP.GPIO1_30 */
			J721E_IOPAD(0x298, PIN_INPUT, 7) /* (AC1) MLB0_MLBSN.GPIO1_31 */
		>;
	};

	/* Pointing to IVP HW */
	mdio_pins_default: mdio_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};

	/* Pointing to IVP HW */
	ext_audio_refclk_pins_default: ext_audio_refclk_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1b4, PIN_INPUT, 4) /* (W25) RGMII6_RD0.AUDIO_EXT_REFCLK3 */
			J721E_IOPAD(0x278, PIN_OUTPUT, 0) /* (T6) RESETSTATz */
			J721E_IOPAD(0x280, PIN_INPUT, 0) /* (U4) SOC_SAFETY_ERRORn */
		>;
	};

	/* Pointing to IVP HW */
	can0_faceplate_pins_default: can0_faceplate_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
			J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
		>;
	};

	/* Pointing to IVP HW */
	can6_faceplate_pins_default: can6_faceplate_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x44, PIN_INPUT, 6) /* (AE24) PRG1_PRU0_GPO16.MCAN6_RX */
			J721E_IOPAD(0x40, PIN_OUTPUT, 6) /* (AC24) PRG1_PRU0_GPO15.MCAN6_TX */
		>;
	};
};

&main_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&can0_faceplate_pins_default>;
	can-transceiver {
		max-bitrate = <5000000>;
	};
};

&main_mcan6 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&can6_faceplate_pins_default>;
	can-transceiver {
		max-bitrate = <5000000>;
	};
};


&davinci_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default>;
	status = "okay";

	//phy0: ethernet-phy@0 {
	//	reg = <0>;
	//	compatible = "ti,davinci_mdio";
	};
//};


&wkup_pmx0 {
	sw11_button_pins_default: sw11_button_pins_default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
		>;
	};
};

&wkup_pmx0 {

	/* Pointing to IVP HW */
	mywkup_debug_pins_default: mywkup_debug_pins_default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x128, PIN_INPUT, 0) /* (C26) EMU0 */
			J721E_WKUP_IOPAD(0x12c, PIN_INPUT, 0) /* (B29) EMU1 */
			J721E_WKUP_IOPAD(0x120, PIN_INPUT, 0) /* (E29) TCK */
			J721E_WKUP_IOPAD(0x124, PIN_INPUT, 0) /* (F24) TRSTn */
		>;
	};

	/* Pointing to IVP HW */
	wkup_gpio_pins_default: wkup_gpio_pins_default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x4, PIN_INPUT, 7) /* (C21) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */
		>;
	};

	/* Pointing to IVP HW */
	wkup_system_pins_default: wkup_system_pins_default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x11c, PIN_OUTPUT, 0) /* (B28) MCU_PORz_OUT */
			J721E_WKUP_IOPAD(0x118, PIN_OUTPUT, 0) /* (C27) MCU_RESETSTATz */
			J721E_WKUP_IOPAD(0x114, PIN_INPUT, 0) /* (D28) MCU_RESETz */
			J721E_WKUP_IOPAD(0x110, PIN_INPUT, 0) /* (D27) MCU_SAFETY_ERRORn */
			J721E_WKUP_IOPAD(0x10c, PIN_OUTPUT, 0) /* (G23) PMIC_POWER_EN1 */
			J721E_WKUP_IOPAD(0x174, PIN_INPUT, 0) /* (J24) PORz */
			J721E_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (C28) RESET_REQz */
		>;
	};
};



&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	status = "disabled";
};

/* Pointing to IVP HW */
&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_backplane_coex61_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
	status = "okay";
};

/* Pointing to IVP HW */
&main_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_backplane_coex60_pins_default>;
	power-domains = <&k3_pds 278 TI_SCI_PD_SHARED>;
	status = "okay";
};

/* Pointing to IVP HW */
&main_uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_bckplane_coex70_pins_default>;
	power-domains = <&k3_pds 279 TI_SCI_PD_SHARED>;
	status = "okay";
};

/* Pointing to IVP HW */
&main_uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_backplane_rif0_pins_default>;
	power-domains = <&k3_pds 280 TI_SCI_PD_SHARED>;
	status = "okay";
};

/* Pointing to IVP HW */
&main_uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_backplane_rif1_pins_default>;
	power-domains = <&k3_pds 281 TI_SCI_PD_SHARED>;
	status = "okay";
};

&main_uart5 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart6_switch_mgmt_pins_default>;
	power-domains = <&k3_pds 283 TI_SCI_PD_SHARED>;
	status = "okay";
};

&main_uart7 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart7_ftdi_pins_default>;
	power-domains = <&k3_pds 284 TI_SCI_PD_SHARED>;
	status = "okay";
};

&main_uart8 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart8_backplane_coex71_pins_default>;
	power-domains = <&k3_pds 285 TI_SCI_PD_SHARED>;
	status = "okay";
};

&main_uart9 {
	/* UART not brought out */
	status = "disabled";
};

&main_gpio2 {
	status = "disabled";
};

&main_gpio3 {
	status = "disabled";
};

&main_gpio4 {
	status = "disabled";
};

&main_gpio5 {
	status = "disabled";
};

&main_gpio6 {
	status = "disabled";
};

&main_gpio7 {
	status = "disabled";
};

&wkup_gpio1 {
	status = "disabled";
};

&mailbox0_cluster0 {
	interrupts = <436>;

	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster1 {
	interrupts = <432>;

	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster2 {
	interrupts = <428>;

	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster3 {
	interrupts = <424>;

	mbox_c66_0: mbox-c66-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_c66_1: mbox-c66-1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster4 {
	interrupts = <420>;

	mbox_c71_0: mbox-c71-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster5 {
	status = "disabled";
};

&mailbox0_cluster6 {
	status = "disabled";
};

&mailbox0_cluster7 {
	status = "disabled";
};

&mailbox0_cluster8 {
	status = "disabled";
};

&mailbox0_cluster9 {
	status = "disabled";
};

&mailbox0_cluster10 {
	status = "disabled";
};

&mailbox0_cluster11 {
	status = "disabled";
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
};

&mcu_r5fss0_core1 {
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
};

&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
};

&main_r5fss0_core1 {
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
};

&main_r5fss1_core0 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
};

&main_r5fss1_core1 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
};

&c66_0 {
	mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
};

&c66_1 {
	mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
};

&c71_0 {
	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
};


&tscadc0 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&tscadc1 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&dss {
	status = "ok";
};

&dss_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;

		dpi_out_real0: endpoint {
			remote-endpoint = <&dp_bridge_input>;
		};
	};
};

&mhdp {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&dp0_pins_default>;
};

&dp0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dp_bridge_input: endpoint {
			remote-endpoint = <&dpi_out_real0>;
		};
	};

	port@1 {
		reg = <1>;
		dp_bridge_output: endpoint {
			remote-endpoint = <&dp_connector_in>;
		};
	};
};

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	exp1: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	exp2: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;

		p09 {
			/* P11 - MCASP/TRACE_MUX_S0 */
			gpio-hog;
			gpios = <9 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "MCASP/TRACE_MUX_S0";
		};

		p10 {
			/* P12 - MCASP/TRACE_MUX_S1 */
			gpio-hog;
			gpios = <10 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "MCASP/TRACE_MUX_S1";
		};
	};
};

&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_msp_pins_default>;
	clock-frequency = <400000>;

	exp4: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_i2c1_exp4_pins_default>;
		interrupt-parent = <&main_gpio1>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;

		p0 {
			/* P0 - DP0_PWR_SW_EN */
			gpio-hog;
			gpios = <0 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "DP0_PWR_SW_EN";
		};
	};
};

&k3_clks {
	/* Confiure AUDIO_EXT_REFCLK2 pin as output */
	pinctrl-names = "default";
	pinctrl-0 = <&ext_audio_refclk_pins_default>;
};

&main_i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c3_pins_default>;
	clock-frequency = <400000>;

	exp3: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pcm3168a_1: audio-codec@44 {
		compatible = "ti,pcm3168a";
		reg = <0x44>;

		#sound-dai-cells = <1>;

		reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;

		/* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
		clocks = <&k3_clks 157 371>;
		clock-names = "scki";

		/* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
		assigned-clocks = <&k3_clks 157 371>;
		assigned-clock-parents = <&k3_clks 157 400>;
		assigned-clock-rates = <24576000>; /* for 48KHz */

		VDD1-supply = <&vsys_3v3>;
		VDD2-supply = <&vsys_3v3>;
		VCCAD1-supply = <&vsys_5v0>;
		VCCAD2-supply = <&vsys_5v0>;
		VCCDA1-supply = <&vsys_5v0>;
		VCCDA2-supply = <&vsys_5v0>;
	};
};

&main_i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c6_pins_default>;
	clock-frequency = <400000>;

	exp5: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&main_i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_slot7_5_pins_default>;
	clock-frequency = <400000>;

};

&main_i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_des_pins_default>;
	clock-frequency = <400000>;

};

&main_i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_audio_adc_pins_default>;
	clock-frequency = <400000>;

};

&main_i2c5 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c5_avb_clk_pins_default>;
	clock-frequency = <400000>;

};

&main_sdhci0 {
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	/* Unused */
	status = "disabled";
};


&main_sdhci2 {
	/* Unused */
	status = "disabled";
};

&serdes0 {
	serdes0_pcie_link: link@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>;
		status = "disabled";
	};
};

&serdes1 {
	serdes1_pcie_link: link@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
		status = "disabled";
	};
};

&serdes2 {
	serdes2_pcie_link: link@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};
};

&pcie0_rc {
	reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie_phy";
	num-lanes = <1>;
	status = "disabled";
};

&pcie1_rc {
	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
	phys = <&serdes1_pcie_link>;
	phy-names = "pcie_phy";
	num-lanes = <2>;
	status = "disabled";
};

&pcie2_rc {
	reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
	phys = <&serdes2_pcie_link>;
	phy-names = "pcie_phy";
	num-lanes = <2>;
};

&pcie0_ep {
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie_phy";
	num-lanes = <1>;
	status = "disabled";
};

&pcie1_ep {
	phys = <&serdes1_pcie_link>;
	phy-names = "pcie_phy";
	num-lanes = <2>;
	status = "disabled";
};

&pcie2_ep {
	phys = <&serdes2_pcie_link>;
	phy-names = "pcie_phy";
	num-lanes = <2>;
	status = "disabled";
};

&pcie3_rc {
	status = "disabled";
};

&pcie3_ep {
	status = "disabled";
};

&serdes_ln_ctrl {
	idle-states = <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
		      <SERDES3_LANE0_PCIE3_LANE0>, <SERDES3_LANE1_PCIE3_LANE1>;
};

&serdes3 {
	serdes3_pcie_link: link@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
	};
};

&serdes4 {
	status = "disabled";
};

&serdes_wiz0 {
	status = "disabled";
};

&serdes_wiz1 {
	status = "disabled";
};

&serdes_wiz4 {
	status = "disabled";
};


&usbss0 {
	ti,vbus-divider;
	ti,usb2-only;
};

&usb0 {
	dr_mode = "host";
	maximum-speed = "high-speed";
};

&usbss1 {
	ti,usb2-only;
};

&usb1 {
	dr_mode = "host";
	maximum-speed = "high-speed";
};

&main_mcan1 {
	status = "disabled";
};

&main_mcan2 {
	status = "disabled";
};

&main_mcan3 {
	status = "disabled";
};

&main_mcan4 {
	status = "disabled";
};

&main_mcan5 {
	status = "disabled";
};

&main_mcan7 {
	status = "disabled";
};

&main_mcan8 {
	status = "disabled";
};

&main_mcan9 {
	status = "disabled";
};

&main_mcan10 {
	status = "disabled";
};

&main_mcan11 {
	status = "disabled";
};

&main_mcan12 {
	status = "disabled";
};

&main_mcan13 {
	status = "disabled";
};


/* Pointing to IVP HW */
&main_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio0_pins_default &debug_pins_default>;
	power-domains = <&k3_pds 105 TI_SCI_PD_SHARED>;
	status = "okay";

	p84 {
		gpio-hog;
		gpios = <84 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "MCAN0_STB";
	};

	p125 {
		gpio-hog;
		gpios = <125 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "MCAN6_STB";
	};
};

/* Pointing to IVP HW */
&main_gpio1 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio1_pins_default>;
	power-domains = <&k3_pds 106 TI_SCI_PD_SHARED>;
	status = "okay";
};

/* Pointing to IVP HW */
&wkup_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_gpio_pins_default &mywkup_debug_pins_default &wkup_system_pins_default>;
	power-domains = <&k3_pds 113 TI_SCI_PD_SHARED>;
	status = "okay";
};