DMSC_Cortex_M3_0: GEL Output: Debugging disabled.
DMSC_Cortex_M3_0: GEL Output: Reading off all PLLs configuration.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80680008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80680038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80680030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80680034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000001
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00001000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80681008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80681038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80681030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80681034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000002
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00002000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80682008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80682038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80682030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80682034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 3 (CPSW5X PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000003
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00003000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80683008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80683038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80683030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80683034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 4 (Audio 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000004
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00004000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80684008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80684038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80684030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80684034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 7 (MSMC PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000007
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00007000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80687008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80687038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80687030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80687034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000008
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00008000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80688008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80688038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80688030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80688034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000C
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000C000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x8068C008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x8068C038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x8068C030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x8068C034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000E
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000E000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x8068E008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x8068E038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x8068E030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x8068E034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x40D00000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x60D00008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x60D00038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x60D00030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x60D00034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off MCU PLL 1 (MCU Peripheral PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x40D00000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000001
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00001000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x60D01008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x60D01038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x60D01030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x60D01034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off MCU PLL 2 (MCU CPSW PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x40D00000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000002
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00002000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x60D02008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x60D02038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x60D02030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x60D02034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Reading off all PLLs configuration ...done.