REM ******************************************* REM CF CONFIGURATION REM ******************************************* REM Halt processor firstly before implement the CF options HA CF TAR AM3358 ; OPERATION CF VECTOR IGNORE ; OPERATION CF SB SB ; OPERATION CF RST YES ; OPERATION CF TRESET ACTIVE ; OPERATION CF HRESET ENABLE ; OPERATION CF CMDRST BOTH ; OPERATION CF INVCI YES ; OPERATION CF SPOWER YES ; OPERATION CF RTP NO ; OPERATION CF TRPEXP BREAKPOINTONLY ; OPERATION CF LENDIAN YES ; OPERATION CF CLK 16 ; OPERATION CF FRZ 1 ; OPERATION CF TGTCONS BDM ; OPERATION CF WSPACE 40300000 F000 ; OPERATION CF RPL 10 ; OPERATION CF BL DISABLE ; OPERATION CF MMU DISABLE ; OPERATION CF CSD ENABLE ; OPERATION CF INCOLD NO ; OPERATION REM ******************************************* REM SC CONFIGURATION REM ******************************************* SC GRP ERASE REM ******************************************* REM System control and configuration registers REM ******************************************* rem copy this from AM335x_EVM_DDR2_LE.reg REM ******************************************* REM PIN MUX control and configuration registers REM ******************************************* rem get these register settings from the pinmux tool REM *********************************************** REM General-Purpose Memory Controller (GPMC) REM *********************************************** rem to match your hardware REM ******************************************* REM MMU control and configuration registers REM ******************************************* rem copy this from AM335x_EVM_DDR2_LE.reg REM ******************************************* REM Cache control and configuration registers REM ******************************************* rem copy this from AM335x_EVM_DDR2_LE.reg REM ******************************************* REM Debug access to caches and TLB registers REM ******************************************* rem copy this from AM335x_EVM_DDR2_LE.reg REM ******************************************* REM PLE control and configuration registers REM ******************************************* rem copy this from AM335x_EVM_DDR2_LE.reg REM ******************************************* REM System performance monitor registers REM ******************************************* rem copy this from AM335x_EVM_DDR2_LE.reg REM ******************************************* REM VFP/NEON registers REM ******************************************* rem copy this from AM335x_EVM_DDR2_LE.reg REM ******************************************* REM STOP WDT2 REM ******************************************* rem copy this from AM335x_EVM_DDR2_LE.reg REM *********************** REM CM_PER, CM_WKUP, CM_RTC REM *********************** REM Configure MPU PLL: rem SCGA CM_WKUP CM_CLKMODE_DPLL_MPU 44E00488 00000004 CM_WKUP SCGA CM_WKUP CM_CLKSEL_DPLL_MPU 44E0042C 00025817 CM_WKUP SCGA CM_WKUP CM_DIV_M2_DPLL_MPU 44E004A8 00000001 CM_WKUP SCGA CM_WKUP CM_CLKMODE_DPLL_MPU 44E00488 00000007 CM_WKUP REM Configure CORE DLL: rem SCGA CM_WKUP CM_CLKMODE_DPLL_CORE 44E00490 00000004 CM_WKUP SCGA CM_WKUP CM_CLKSEL_DPLL_CORE 44E00468 0003E817 CM_WKUP SCGA CM_WKUP CM_DIV_M4_DPLL_CORE 44E00480 0000000A CM_WKUP SCGA CM_WKUP CM_DIV_M5_DPLL_CORE 44E00484 00000008 CM_WKUP SCGA CM_WKUP CM_DIV_M6_DPLL_CORE 44E004D8 00000004 CM_WKUP SCGA CM_WKUP CM_CLKMODE_DPLL_CORE 44E00490 00000007 CM_WKUP REM Configure PERipheral DLL: rem SCGA CM_WKUP CM_CLKMODE_DPLL_PER 44E0048C 00000004 CM_WKUP SCGA CM_WKUP CM_CLKSEL_DPLL_PER 44E0049C 0403C017 CM_WKUP SCGA CM_WKUP CM_DIV_M2_DPLL_PER 44E004AC 00000005 CM_WKUP SCGA CM_WKUP CM_CLKSEL_DPLL_PERIPH 44E0049C 04012F17 CM_WKUP SCGA CM_WKUP CM_CLKMODE_DPLL_PER 44E0048C 00000007 CM_WKUP REM Configure DDR DLL: rem SCGA CM_WKUP CM_CLKMODE_DPLL_DDR 44E00494 00000004 CM_WKUP SCGA CM_WKUP CM_CLKSEL_DPLL_DDR 44E00440 00012F17 CM_WKUP SCGA CM_WKUP CM_DIV_M2_DPLL_DDR 44E004A0 00000001 CM_WKUP SCGA CM_WKUP CM_CLKMODE_DPLL_DDR 44E00494 00000007 CM_WKUP REM ******************************************* REM DDR_SETUP DDR3_EMIF_Config() REM ******************************************* REM (from Enable_VTT_Regulator()): SCGA DDR_SETUP CTRL_PADCNF_ECAP0_IN_PWM0_OUT 44E10964 0000000F DDR_SETUP /hide SCGA DDR_SETUP CM_WKUP_GPIO0_CLKCTRL 44E00408 00040002 DDR_SETUP /hide rem Wait until bits [17:16] of the CM_WKUP_GPIO0_CLKCTRL register are “00” indicating GPIO0 is fully functional rem Wait until bit [8] of the CM_WKUP_CLKSTCTRL register is set (‘1’) indicating clock is active SCGA DDR_SETUP GPIO_SYSCONFIG 44E07010 00000002 DDR_SETUP /hide rem Wait for bit[0] of the GPIO0_SYSSTATUS register to be set (‘1’) indicating soft reset complete SCGA DDR_SETUP GPIO_CTRL 44E07130 00000000 DDR_SETUP /hide SCGA DDR_SETUP GPIO_SETDATAOUT 44E07194 00000080 DDR_SETUP /hide SCGA DDR_SETUP GPIO_OE 44E07134 FFFFFF7F DDR_SETUP /hide rem (from EMIF_PRCM_CLK_ENABLE()): rem (is this an actual register?) SCGA CM_WKUP unidentified_register 44E000D0 00000002 DDR_SETUP /hide SCGA DDR_SETUP CM_PER_EMIF_CLKCTRL 44E00028 00000002 DDR_SETUP /hide rem Wait until bits [17:16] of the CM_PER_EMIF_CLKCTRL register are “00” indicating module is fully functional rem (from VTP_Enable()): SCGA DDR_SETUP VTP_CTRL 44E10E0C 00000000 DDR_SETUP /hide SCGA DDR_SETUP VTP_CTRL 44E10E0C 00000006 DDR_SETUP /hide SCGA DDR_SETUP VTP_CTRL 44E10E0C 00000046 DDR_SETUP /hide SCGA DDR_SETUP VTP_CTRL 44E10E0C 00000046 DDR_SETUP /hide SCGA DDR_SETUP VTP_CTRL 44E10E0C 00000047 DDR_SETUP /hide rem Wait for bit[5] of the VTP_CTRL register to be set rem (from PHY_Config_CMD()): SCGA DDR_SETUP CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 44E1201C 00000040 DDR_SETUP /hide SCGA DDR_SETUP CMD0_REG_PHY_INVERT_CLKOUT 44E1202C 00000001 DDR_SETUP /hide SCGA DDR_SETUP CMD1_REG_PHY_CTRL_SLAVE_RATIO_0 44E12050 00000040 DDR_SETUP /hide SCGA DDR_SETUP CMD1_REG_PHY_INVERT_CLKOUT 44E12060 00000001 DDR_SETUP /hide SCGA DDR_SETUP CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 44E12084 00000040 DDR_SETUP /hide SCGA DDR_SETUP CMD2_REG_PHY_INVERT_CLKOUT 44E12094 00000001 DDR_SETUP /hide rem (from PHY_Config_DATA()): rem Perform the "AM335x DDR PHY register configuration for DDR3 using Software Leveling" process to determine values for these SCGA DDR_SETUP DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0 44E120C8 0000003A DDR_SETUP /hide SCGA DDR_SETUP DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 44E120DC 000000BD DDR_SETUP /hide SCGA DDR_SETUP DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0 44E12108 00000102 DDR_SETUP /hide SCGA DDR_SETUP DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0 44E12120 000000F3 DDR_SETUP /hide SCGA DDR_SETUP DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0 44E1216C 0000003A DDR_SETUP /hide SCGA DDR_SETUP DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0 44E12180 000000BD DDR_SETUP /hide SCGA DDR_SETUP DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0 44E121AC 00000102 DDR_SETUP /hide SCGA DDR_SETUP DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0 44E121C4 000000F3 DDR_SETUP /hide rem (from main DDR3_EMIF_Config() function): SCGA DDR_SETUP ddr_cmd0_ioctrl 44E11404 0000018B DDR_SETUP /hide SCGA DDR_SETUP ddr_cmd1_ioctrl 44E11408 0000018B DDR_SETUP /hide SCGA DDR_SETUP ddr_cmd2_ioctrl 44E1140C 0000018B DDR_SETUP /hide SCGA DDR_SETUP ddr_data0_ioctrl 44E11440 0000018B DDR_SETUP /hide SCGA DDR_SETUP ddr_data1_ioctrl 44E11444 0000018B DDR_SETUP /hide SCGA DDR_SETUP ddr_io_ctrl 44E10E04 00000000 DDR_SETUP /hide SCGA DDR_SETUP ddr_cke_ctrl 44E1131C 00000001 DDR_SETUP /hide SCGA DDR_SETUP DDR_PHY_CTRL_1 4C0000E4 00000006 DDR_SETUP /hide SCGA DDR_SETUP DDR_PHY_CTRL_1_SHDW 4C0000E8 00000006 DDR_SETUP /hide SCGA DDR_SETUP DDR_PHY_CTRL_2 4C0000EC 00000006 DDR_SETUP /hide SCGA DDR_SETUP SDRAM_TIM_1 4C000018 0888A3AB DDR_SETUP /hide SCGA DDR_SETUP SDRAM_TIM_1_SHDW 4C00001C 0888A3AB DDR_SETUP /hide SCGA DDR_SETUP SDRAM_TIM_2 4C000020 2651269A DDR_SETUP /hide SCGA DDR_SETUP SDRAM_TIM_2_SHDW 4C000024 2651269A DDR_SETUP /hide SCGA DDR_SETUP SDRAM_TIM_3 4C000028 501F84EF DDR_SETUP /hide SCGA DDR_SETUP SDRAM_TIM_3_SHDW 4C00002C 501F84EF DDR_SETUP /hide SCGA DDR_SETUP SDRAM_REF_CTRL 4C000010 0000093B DDR_SETUP /hide SCGA DDR_SETUP SDRAM_REF_CTRL_SHDW 4C000014 0000093B DDR_SETUP /hide SCGA DDR_SETUP ZQ_CONFIG 4C0000C8 50074BE4 DDR_SETUP /hide SCGA DDR_SETUP SDRAM_CONFIG 4C000008 61C04B32 DDR_SETUP /hide SCGA DDR_SETUP control_emif_sdram_config 44E10110 61C04B32 DDR_SETUP /hide REM ******************************************* REM CF GROUP CONFIGURATION REM ******************************************* CF GRP SYSCOP ENABLED ; GROUP CF GRP PINMUX ENABLED ; GROUP CF GRP CM_WKUP ENABLED ; GROUP CF GRP GPMC ENABLED ; GROUP CF GRP MMU DISABLED ; GROUP CF GRP CACHE DISABLED ; GROUP CF GRP DEBUG DISABLED ; GROUP CF GRP PLE DISABLED ; GROUP CF GRP PERFMON DISABLED ; GROUP CF GRP VFP_DOUBLE DISABLED ; GROUP CF GRP VFP_SINGLE DISABLED ; GROUP CF GRP VFP_CTRL DISABLED ; GROUP CF GRP WDT_STOP DISABLED ; GROUP CF GRP DDR_SETUP ENABLED ; GROUP REM ******************************************* REM BL CONFIGURATION REM ******************************************* REM ******************************************* REM MMUOS CONFIGURATION REM ******************************************* REM ******************************************* REM TF CONFIGURATION REM ******************************************* REM ******************************************* REM END.... REM *******************************************